During the transition to STM32_CLOCK macro (in 57723cf), the `clocks`
property of peripherals requiring more than one bit to be set were
mistakenly modified. Commit 2c3294b079
partially fixed these errors, but some nodes for the U5 series are still
wrong.
Restore `clocks` on affected devices in corresponding STM32U5 DTSI.
Fixes: 57723cf405
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Add information on CANFD dllclk upper and lower limits on these SoCs:
- RA8: RA8M1, RA8D1, RA8T1
- RA6: RA6E2
- RA4: RA4E2
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
This commit adds basic support for KSZ8463/KSZ8463F chips to the
dsa_ksz8xxx.c driver.
These chips have limited register compatibility with other members
of the KSZ8XXX family - their registers are 16 bits wide as opposed
to the 8-bit registers supported by the driver for KSZ8794 and
KSZ8863. Following the general logic of the existing code,
the 16-bit registers of KSZ8463 are split into 8-bit halves.
For the KSZ8463F chip, it is assumed that both ports are used
in Fiber mode.
A new configuration option, CONFIG_DSA_KSZ_PORT_ISOLATING, has been
added to isolate traffic between DSA slave ports.
The driver has been tested on a custom board with an STM32F7 SoC.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Set pm device runtime runtime auto flag to ensure saadc instances
are initialized correctly if pm device runtime is used.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This commit adds MBOX device tree entry for RT1180.
Adds functions to copy and boot CM7 core.
Adds MPU region for shared memory without caching.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
This reverts commit 70419bdee7.
This is because there are issues around slow IPC thoughput
with icbmsg, which is causing issues with BLE when lots of
data is required to be exchanged, e.g. with ISO.
Also there is an assert icmsg.c#L190 which occurs when
initializing bluetooth and IPC in certain circumstances.
Signed-off-by: Sean Madigan <sean.madigan@nordicsemi.no>
In some cases, CPUs that may need to reset or
temporary stop communication. This commit adds "unbound"
functionality that provides a callback to IPC service user
when connection was interrupted for some reason, e.g.
expected or unexpected CPU reset, closing the
endpoint. The "unbound" callback is optional to implement
by endpoints. This commit implements it in the ICMsg
backend.
Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
STM32N6 ADC doesn't have an integrated prescaler, so these properties have
to be removed.
Though the F1 compatible also removes these two same properties, grouping
the N6 with the F1 would not be convenient since there are lots of
differences between the two.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The current implementation requires SoCs/Boards to manualy instantiate
the preripherals and initilize them.
The change lets Zephyr rely on the device tree setup to instantiate &
initialize the relevant gpio peripheral.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Add OTGFS peripheral to the stm32h7rs soc series, and enable it on the
Discovery board STM32H7S78-DK, where it is wired to USB Type-C port 2.
Signed-off-by: Titouan Christophe <moiandme@gmail.com>
First commit to add support for USBFS module on Renesas RA
- Remove renesas,ra-usb binding
- Add 2 new binding for Renesas RA USBFS and USBHS
- Remove unused interrupts of USBHS
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
This PR adds support for Maxim Integrated
DS1337 RTC chip.
Supported functionalities:
* Alarm interrupt (both alarms trigger INTA pin)
* Time setting/reading
* Both alarms setting/reading
* SQW frequency configuration
Tested on nRF52833-DK using rtc_api test set.
Signed-off-by: Marcin Lyda <elektromarcin@gmail.com>
This Introduces a driver for the i2c interface of Phosense XBR818.
XBR818 is a 10.525Ghz Radar chip with builtin detection algorithm.
Signed-off-by: Camille BAUD <mail@massdriver.space>
CAN is not ready yet for this platform (clock control drivers). So
remove the nodes for now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This driver triggers the TURN_ON and TURN_OFF actions for certain
power states. These power states are specified via device tree.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add Clock Control driver support for Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
