This peripheral combines a hardware-based USB CDC ACM serial interface
and a JTAG interface.
It is present in the ESP32-C3.
Signed-off-by: Martin Jäger <martin@libre.solar>
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().
This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
This will add ace compatible DMA driver.
Co-authored-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This adds basic support for the watchdog timer on the RP2040 MCU and
Raspberry Pi Pico development board
Signed-off-by: Jamie McCrae <spam@helper3000.net>
This commit adds support for the ds18b20 1-wire temperature sensor.
The sampling resolution of the sensor can be set in DT.
In case only a single device is on the bus, the driver issues
skip_rom commands. However, in case DT defines several devices,
the driver will use match_rom commands and therefore it is necessary
to set the rom_id of the device via the sensor attribute interface before
being able to sample sensor values.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The zephyr-serial w1 driver introduced in this commit implements
all routines for the w1 api on top of the zephyr serial driver.
W1 bit read, write, and reset operations are executed by issuing
polling zephyr serial byte read and write operations.
The driver should be usable on most platforms in zephyr that have
implemented support for the polling procedures of the serial driver.
As not all serial drivers are implemented exactly the same minor
additional quirks may be needed on some platforms.
The most notable difference of polling serial driver implementations
seems to be that some return immediately from poll_out after the
transmission was started(e.g. STM32) and others wait until
the transmission was completed before returning from poll_out
(e.g. NRF). While this has influence on the timeout, both types
are supported by this driver because the driver waits for a
configurable time period until it terminates the read.
The driver needs an appropriate open drain interface to be able
to communicate with slaves.
In the simpliest case this might be achived by configuring the mcu pins
in open-drain configuration with a (sufficiently small) pull-up to 3V3/5V.
Otherwise an external circuit needs to provide this interface.
Overdrive and Standard Speed modes are supported by this driver.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit introduces a new api for the Dallas 1-wire protocol.
The api includes link functions for read and write operations on
bit, byte, and block level, as well as functions to reset and
lock the bus.
The bus configuration is derived from the device tree and can be
queried using w1_slave_count routine.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This patch is to enhance the uart ns16550 driver to get clock frequency
from clock manager or devicetree if clock_frequency is defined.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
The default S0S1 drive setting is not suitable for TWI/TWIM pins.
Override it with S0D1 as for some SoCs (e.g. nRF52833) without
this the peripheral will not work properly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This mirrors #36499 and other PRs that added them for other
architectures.
This silences a large number of dtc warnings due to the missing
property. It seems reasonable to require an address-cells property since
any interrupt controller could be the parent of an interrupt-map.
The only device actually using interrupt-maps is neorv32, and it needs
an address-cells of 2 (since this is the default if none is specified it
worked like that before this change).
While I touched this, I reordered the properties for consistency across
boards, but there's a lot of variance here already.
Signed-off-by: Olof Johansson <olof@lixom.net>
There is no driver or other references to the zephyr,ipm-console
devicetree compatiable. So remove the binding.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add binding for zephyr sdmmc disk device, which uses the SD
subsystem to manage an SD memory card.
Fixes#46410Fixes#46266
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When required, add "st,stm32h7-spi" compatible on stm32 compatible
series (today: stm32h7, stm32mp1 and stm32mp1).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a stm32h7 spi compatible.
This compatible intends to match all SPI hardware blocks that
can be compatible with the one available in stm32h7 devices,
for instance, but not limited to stm32u5 and stm32mp1.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use consistent name for SPI HW block property so applications
using a device tree overlay work transparently.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Use consistent name for SPI HW block properties across Microchip
HW, so applications using a device tree overlay work
transparently.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add MKR header connector that is implemented by Arduino MKR series.
This allows hardware with compatible headers to define the related GPIOs.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Some EFR32 SoCs use a secure element subsystem to manage
security features (i.e., TRNG, secure bootloader or cryptographic
functions).
This driver relies on the SE Manager high-level API provided by Silicon
Labs. The API interacts with the SE subsystem, provides helper functions
to achieve cryptographic operations and ensures that only one operation
is running at a time by using mutexes and semaphores.
Instead of relying on the SE Manager from Silicon Labs, one could
recreate the behaviour of the Manager and put the code in the crypto
driver folder and create a dependency for other drivers using the crypto
manager (e.g., keys, entropy).
I went for the SE Manager API as it is already there and supported by
Silicon Labs.
Tested using the random subsystem.
Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
Add the stm32g0 bindings for the HSISYS to be used with the hsi divisor
with a factor programmable from 1 to 128.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
The definition of the octospi clock source is given
by the DTS node. The default value selects the sysclk
(not pclk) for the alternate clock control.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The definition of the clock source for the 2 octospi
instances is given by the DTS node.
The default value selects the sysclk (not pclk)
for the alternate clock control.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
According to the formulas found in the reference manuals of the SoC
families using the "st,stm32-temp-cal" version of the temperature sensor
(i.e. G0, G4, H7, L0, L1, L4, L5, U5, WB, WL), the temperature is
computed with the following formula:
T = ((TS_CAL2_TEMP - TS_CAL1_TEMP) / (TS_CAL2 - TS_CAL1))
* (TS_DATA - TS_CAL1) + TS_CAL1_TEMP
What is called ts-cal-offset in the stm32_temp driver is therefore the
same value as TS_CAL1_TEMP1. Use it directly instead of defining another
property.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The stm32_temp driver defines the ts-voltage-mv property to determine
the reference voltage of the ADC in the temperature computation. However
this information is already available in the device tree at the ADC
level (even with the same default value). Use it through the ADC API
instead of duplicating the information.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This new DTS Node is defining a ratio for Vbat internal
bridge of monitoring sensor connected
to a ADC internal channel. The voltage reference value
is given by the ADC of the stm32.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Like other temperature or vrefint sensor, the stm32 mcu
also have a Vbat monitoring internal channels on ADC.
Add this entry to the device tree.
The vref is usually 3300mV present on the target board.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
-pin properties, e.g. tx-pin have been replaced by pinctrl. Mark them as
deprecated since old pin configuration schemes will be deprecated in
Zephyr 3.2.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit moves the hardware configuration for ledc
peripheral to the device-tree instead of Kconfig.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pin control support for SWO log backend, by creating a new
ITM node for the ARM instrumentation trace macrocell. Add pin control
properties under this node, and refactor the swo-req-freq property to be
defined within this node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add devicetree node for the pinctrl of the Xilinx Zynq-7000 series. Pinctrl
is set through a subset of the System Level Control Registers (SLCR), which
is accessed through the syscon driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
