start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Pass the function argument `dev` to the async callback instead of
`data->uart_dev`. The pointers are identical, but `dev` is already
available in this context, so it's clearer to use it directly.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Add Ethernet support including:
- Board initialization code with PHY reset handling
- Device tree definitions for ethernet
- PHY link state tracking fixes in ethernet driver
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Create option CONFIG_CRC_STM32_DMA_THRESHOLD used to select between CPU and
DMA copy based on buffer size. Depending on the application and hardware,
it can be faster to perform a CPU copy for small buffer sizes than request
a DMA transfer: this options allows limiting DMA usage only to buffers of a
large enough size.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a new driver for the STM32 CRC. The driver is instance-aware and
supports data transfers using DMA.
Co-authored-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Allocating buffer in response to control transfer is part of processing
and therefore should not be done in UDC driver but rather in the stack.
Simplify UDC driver design by moving all control transfer buffer
allocations and processing to USB stack.
New control transfer handling flow is as follows:
1. USB stack allocates and queues buffer for Setup stage. This informs
UDC driver that USB stack is ready to process new transfer.
2. UDC driver completes enqueued Setup buffer. SETUP data may have
been received by device before Setup buffer was enqueued.
If multiple SETUP data was received, UDC driver must complete
request using last received SETUP data.
3. USB stack processes request. USB stack is responsible for:
* Stalling control endpoint when request cannot be processed
* Allocating and enqueueing Data stage buffer if necessary
- Depending on enqueued endpoint (IN/OUT), UDC driver is
expected to complete the transfer. If host sends new SETUP
data for any reason (e.g. timeout), then Data stage buffer
must be completed with -ECONNRESET code.
- UDC driver may postpone processing Data IN until USB stack
enqueues new Setup stage buffer.
* Handling status stage if applicable
- If Data IN was enqueued, stack immediately allocates and
enqueues Status OUT stage buffer.
- If Data OUT was enqueued, stack waits for Data OUT buffer
completion before doing any further processing.
- If control transfer handling fails, stack is expected to
STALL control endpoint.
* Allocating and enqueuing Setup buffer.
- This informs UDC driver that stack has finished processing
control transfer. UDC driver may choose to start processing
Data IN and/or Status OUT only after new Setup buffer is
enqueued.
4. UDC driver must fail (complete with -ECONNRESET) any enqueued and
not completed Data and Status buffers if host sends new SETUP data.
UDC driver must be able to buffer last received SETUP data until
USB stack is ready (enqueues Setup buffer).
5. UDC driver must complete all Data and Status buffers before it
completes Setup buffer.
6. UDC driver may keep ownership of Setup, Data and/or Status buffers
across USB bus resets. USB stack does not attempt to dequeue any
control transfer buffer it enqueued.
This approach implicitly synchronizes UDC driver against USB stack,
which ensures that only one set of Setup/Data/Status buffers is
allocated at a time.
Another advantage of the rework is drawing a clear line on buffer
ownership. The buffer responsibilities are as follows:
* USB stack is the only entity that both allocates and frees the
buffers. Only USB stack is allowed to set "setup", "data" and
"status" fields in struct udc_buf_info.
* UDC takes ownership of buffers handed to it in udc_ep_enqueue().
* UDC releases buffer ownership by calling udc_submit_ep_event().
Because there is just a single place where the buffer ownership changes,
and all buffers must go USB stack (alloc) -> UDC (perform requests on
the bus) -> USB stack (free) route it would be possible in the future to
implement a "tap" similar to Linux usbmon that would ease debugging.
This commit significantly changes how USB stack communicates with UDC
drivers. It was decided that supporting both the old and new model
simultaneously would require way too much effort. Therefore all UDC
drivers were reworked. Following people worked on driver rework:
* Tomasz Moń - ambiq, dwc2, kinetis, mcux ip3511, nrf, numaker,
renesas ra, rpi pico, smartbond, virtual
* Mathieu Choplain - stm32
* Mark Wang - mcux ehci
* Johann Fischer - sam0, stm32
* Ren Chen - it82xx2
* Brandon Hurst - max32
* Gerson Fernando Budke - sam udp, sam usbc, sam usbhs
Co-authored-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Co-authored-by: Mark Wang <yichang.wang@nxp.com>
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Co-authored-by: Ren Chen <Ren.Chen@ite.com.tw>
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Co-authored-by: Brandon Hurst <brandon.hurst@analog.com>
Signed-off-by: Brandon Hurst <brandon.hurst@analog.com>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Ble host and link layer threads initialization is no more done
during the system initialization.
Add stm32wba_ble_ctlr_thread_init() and
stm32wba_ll_ctlr_thread_init() functions calls
during ble and ieee802.15.4 driver initialization
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
In calculation of the FREQUENCY register value take into account
the tolerance of the peripheral clock to ensure that the SCL
frequency does not exceed the specified value.
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
The nocache memory may not be freed when the `transferSofar` is 0, it
is allocated when (transferBuffer != NULL && transferLength != 0), so
release it with same conditions.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Track success explicitly and only report timeout when no matching PHY ID
was found after all retries.
Extend the Motorcomm YT8521 PHY driver to support YT8531 chip.
The YT8531 is compatible with YT8521 and shares the same register
layout and configuration interface.
- "motorcomm,yt8521" for YT8521
- "motorcomm,yt8531" for YT8531
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
On STM32 HAL2, LL_ICACHE functions expects the ICACHE instance as first
argument. Add a macro that will construct the correct list of arguments
depending on HAL version.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add abstraction function to check the TX/RX fifo flags and enable/disable,
and redefine a few macros (like stop bits or data width) for STM32 HAL2.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Added Silabs Kconfig support for counter driver and implemented the
counter APIs using protimer underneath.
Signed-off-by: sree sreerajatha <sree.sreerajatha@silabs.com>
Fix a typo in `pinctrl_configure_pins` where the variable `pin_cgf`
was used instead of `pin_cfg`. Update all references accordingly.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
ISR bits are set on input level or edge changes, regardless of whether an
interrupt is actually enabled on that line. Therefore, we check whether an
interrupt is actually enabled by masking with IMR. If we didn't do this,
some other enabled interrupt firing could also result in a callback for a
disabled interrupt.
Signed-off-by: Bert Abrath <bert.abrath@basalte.be>
The RX GPIO was originally develop for RX130 MCU which only have port
0 to 5 and A to J, this commit add missing port initialize for other RX
MCU family
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
The ESP32 MCPWM driver does not initialize the pinctrl configuration if
only the capture units of MCPWM are used and no other MCPWM outputs are
used. This leads to pwm capture requests timing out. Fix this by applying
the pinctrl configuration during module initialization.
Signed-off-by: Christopher Smith <christophersmith107@gmail.com>
- Removes the unused items from the device structures for peri clock.
- Removes the now unused `resource-type`, `resource-instance`, and
`resource-channel` binding properties.
- Updates the Migration Guide with removed binding properties.
- Remove the binding properties from board, samples, and test overlays.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
With Bypass enabled, the MCU doesn't work.
Instead, set waydisable to 0xf (all ways disabled), and
disable bypass.
Signed-off-by: Camille BAUD <mail@massdriver.space>
Extend the shared pinctrl driver for BL70XL:
- Use 4 UART signal routing slots (vs 8 on BL60x/BL70x)
- Add XTAL32K pin muxing disable for GPIO30/31
- Handle key scan drive function (disable IE)
- Replace magic numbers with register field defines
- Add BL70XL to pinctrl CMakeLists.txt (reuses bl60x_70x driver)
Signed-off-by: William Markezana <william.markezana@gmail.com>
Fixes the mix-up of HCLK and SYSCLK in h7 clock driver and also makes sure
to calculate the correct startup frequency:
- Take care of bootloader might already have configured clocks instead of
relying on #defines/dts).
- Use HAL HSI_VALUE instead of STM32_HSI_FREQ which can be 0 if hsi node
is disabled in DT (but is default on after reset...)
Also move calculation of old_hclk_freq above set_up_plls() during
stm32_clock_control_init(), which can change the current clock setting and
make it impossible to get the previous clock.
Remove not needed special handling for h7rsx controllers.
Add a comment to the clk_hsi node in the h7x / h7rsx DT stating that the
clock is enabled by default after reset.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Memory W25Q256 support added into flash driver. If someone
uses this memory, the driver will configured into 4-bytes
address mode which will cause issues with the bootROM for
some NXP's RTs/RW microcontrollers.
Signed-off-by: Missael Maciel <davidmissael.maciel@nxp.com>
Fix I2C transaction len using the correct size of the data to be sent
and not the returned length of the allocated buffer.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Brenden Adamczak <cerebralasylum1@gmail.com>
Co-authored-by: Armando Visconti <armando.visconti@st.com>
Fix the representation of pixel formats with an X (unused) or A (alpha)
channel to make the four character match the order in the channels in
memory byte per byte.
These formats are imported from Linux but contain a naming inconsistency.
The four character codes still match the Linux formats from V4L2
include/uapi/linux/videodev2.h based on the byte content rather than the
name: this means that communicating with Linux systems will work, but
sharing source code with Linux will need to modify the variable names.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Nordic's nPM10 Series PMIC Multi-function Device devicetree properties and
driver.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Name the XSPI 1/2 depending on the stm32 series.
It could be mixed between XSPI or OCTOSPI depending
on the module HAL.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Name the XSPI 1/2 depending on the stm32 series. It could be mixed between
XSPI or OCTOSPI depending on the module HAL.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add pm_action callback with PINCTRL_STATE_SLEEP on suspend and
PINCTRL_STATE_DEFAULT on resume. Register the driver with
PM_DEVICE_DT_INST_DEFINE so the PM framework calls the callback
during system sleep transitions.
If no sleep pinctrl state is defined in DTS, the suspend call
is a no-op.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Add Silabs General GPCRC driver for Series 2 boards
Enable crc sample and test cases for Silabs series 2
Tested on real boards and compared result with all CRC16
and CRC32-IEEE algorithm
Signed-off-by: Phuc Hoang <donp172748@gmail.com>
Add initial support for SCMI shell commands. For now, this only includes
clock protocol-related commands. Other SCMI protocols will be added
incrementally.
Part of #103633.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for SCMI transport layer using ARM SMC (Secure Monitor
Call) as the doorbell mechanism with shared memory for data transfer.
Communication is performed synchronously so polling is the only
supported mode. The implementation follows the SCMI specification
for SMC/HVC based transport.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
Add polling_only flag to scmi_channel structure to support transports
that require polling mode (e.g., SMC transport which uses synchronous
SMC/HVC calls without interrupt support).
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
stm32wbxx bump to version to 1.24.0
stm32wlxx bump to version 1.4.0
Update dma_stm32.h to sync with HAL new function prototype for
LL_DMA_IsActiveFlag_HT*() functions that now expect a const pointer
on STM32WLX series.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
