This commit Modifies the DMA STM32 Kconfig to enable shared IRQ
support for the STM32U0 series.
This change ensures DMA channels with shared IRQs are properly
configured for stm32u0 devices.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
The clock_stm32_ll_common.c function set_up_plls calls
LL_RCC_PLL_Disable();and it was not waiting for the
disable to complete before trying to configure
the pll sysclock which creates a race condition for
pll configuration.The wait for re-enabling the RCC pll
is already there, it was just missing the wait for
the disable before configuration. Also added the wait for PLL2.
Signed-off-by: Benjamin Curtis Byers <ben.byers@ubcobikes.com>
Adapt the stm32 flash driver for the stm32h7rs serie where some
bit of the FLASH registers are named differently from stm32h7 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch will save configured link clock and ensure
ssp starts with xtal clock if ssp ver >= 2.0
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
First commit to add support for gpio interrupt on Renesas RA
- Add support for external interrupt driver
- Add support for gpio interrupt config
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
create rampstat Kconfig template to enable respective tmc drivers to
reuse the common configurations
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Convert vendor specific **_WIFI_BUILD_ONLY_MODE symbol as global
in order to provide common build flag to enable CI with no blobs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
ADS131M02 is Texas Instruments 2-channel, 24-Bit differential
input ADC which support wide range datarate.
Driver add support for adc read, channel configure, adc sampling
mode configuration and power management.
[1]. https://www.ti.com/lit/ds/symlink/ads131m02.pdf
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
config->base is already defined as ADC_TypeDef so no there is no need to
cast it as such. Remove all occurrences throughout the file.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that clock source and sequencer are defined with strings in device
tree, move the old defines directly in the driver
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that st,adc-sequencer and st,adc_clock-source use a string, update the
ADC driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
fu drv adc update driver with string
Remove specific cases for H7 and U5: group them together and only call a
single function. ADC3 of H72x/H73x and ADC4 of U5 are different from other
ADC of their series, and have dedicated functions in the LL for enabling
DMA, but they're doing the exact same operation as
LL_ADC_REG_SetDataTransferMode.
Incidentally, this change allows H7A/H7B to use the DMA (it seems to have
been missed before).
Last, this change enables the DMA support for F1x ADC.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32F3 and H7 have multiple ADC versions difficult to differentiate.
Use clearer macros to make code more readable.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use shell_device_get_binding() instead of device_get_binding() so that
we get the device based on its name and in addition by its label.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Mode 0 cannot establish a connection when used as a UDP server,
replace mode 0 with mode 2 to save the client's IP and port as
the communication address when a message is received.
Fixes#82898
Signed-off-by: Hongquan Li <hongquan.prog@gmail.com>
- Add "channel-available-mask" property in ADC node
to detect which channels are available to use
- Add "add-average-count" property in ADC node to chose
number of count of the addition or average mode
- Change the source code of ADC to match with 2 new properties.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Rename everything from tla2021 to tla202x (except dtcompatible)
in preparation to add support for tla2022 and tla2024
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
Currently, there is a small race window where we can miss an interrupt.
Right after we're done reading the RX buffer but just before decrementing
the RX counter to zero, the ENC28J60 may receive a packet. The chip will
raise an interrupt, but the line is still asserted. That means that the
callback will not be invoked since it is edge-triggered.
To avoid that, disable interrupts on the chip itself before processing
the RX buffer.
In fact, the ENC28J60 datasheet specifically says:
"After an interrupt occurs, the host controller should
clear the global enable bit for the interrupt pin before
servicing the interrupt. Clearing the enable bit will
cause the interrupt pin to return to the non-asserted
state (high). Doing so will prevent the host controller
from missing a falling edge should another interrupt
occur while the immediate interrupt is being serviced.
After the interrupt has been serviced, the global enable
bit may be restored. If an interrupt event occurred while
the previous interrupt was being processed, the act of
resetting the global enable bit will cause a new falling
edge on the interrupt pin to occur."
This is also what is being done in the Linux driver [1].
[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1126
Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
The enc28j60 errata sheet says:
"The Receive Packet Pending Interrupt Flag
(EIR.PKTIF) does not reliably/accurately report
the status of pending packets."
"In the Interrupt Service Routine, if it is unknown if
a packet is pending and the source of the interrupt
is unknown, switch to Bank 1 and check the value
in EPKTCNT.
If polling to see if a packet is pending, check the
value in EPKTCNT."
A workaround has already been implemented inside of eth_enc28j60_rx().
But checking PKTIF before calling eth_enc28j60_rx() completely defeats
the purpose of the workaround. Do not check it.
Moreover, clearing ENC28J60_BIT_EIR_PKTIF is useless since it is
automatically cleared once all packets are read. So remove that check
and clarify comment.
Also please refer to the Linux driver [1].
[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1090
Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
After a non-power reset (wdt) pins may remain in non-default state.
To ensure that a system initialization is the same after any reset,
it is necessary to initialize pins to the default state.
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
Map MMIO memory by using DEVICE_MMIO_NAMED_x() APIs.
And some platforms has no soc.h, so use __has_include to check it
firstly.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
