Hardcode the lookup table for SWDP requests.
This is an optimization to save some space.
Documentation was added to understand the values.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Add API to read count bits from SWDIO into data LSB first.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Move low-level GPIO functions to a separate file and use GPIO driver
API if low-level GPIO support is not available for the platform.
Allows alternative pin configuration using only two pins, clk and dio.
Improve binding description.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add Serial Wire Debug Port interface driver API and bit-bang driver.
The driver requires a simple Hardware Interface Circuits (HICs),
where signals CLK, DOUT, DIN, ENn, OE_ENn, RESETn
are connected to board GPIOs and buffered signals SWD_CLK and SWD_DIO
to the target.
Signal OE_ENn controls the direction of the Serial Wire (SWD_DIO),
ENn the buffers SWD_CLK possibly others and enables/disables HIC.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add the support of the stm32h7rs serie to the flash stm32h7 driver
Remap Flash registers to the stm32h7rs serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce the stm32h7RS serie to the ADC driver,
based on the stm32h7: two ADC 12 resolution
For stm32h7rs ADC calibration, the
LL_ADC_SetCalibrationFactor is not used.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
LPC GPIO binding was wrong in that the reg address
on the simple soc bus was given as an index of the gpio ports
within a gpio controller. Fix this by putting the GPIO node
on the simple bus as a single node with the correct base address,
and make the ports children of this node.
Change the driver to get the port number from the reg address
instead of a custom property, and get base address from DT instead
of the SDK macro definition.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The stm32 flash driver returns success even though
writing failed when instruction cache was enabled.
Fix by not overriding error code when re-enabling
instruction cache.
Signed-off-by: Riku Karjalainen <riku.karjalainen@vaisala.com>
The reason is that this driver needs to call the function
'irq_connect_dynamic()' which is implemented with DYNAMIC_INTERRUPTS.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
TI Dual-Mode timer is used as the arch timer for systick on J721E R5
cores. Add DM Timer for systick timer support.
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
- If status == PROP_ERROR_RXBUF, that means rx buffer head is not empty.
In case of this, RF_EventRxEntryDone is never triggered and thus we
enter an infinite loop of nothing happening. Due to this, TCP socket
times out.
- To fix this, we need to free rx buffer current head. However, it seems
better to free all the elements that are already finished instead of
just head.
- Before 128354ae17, the buffer was reset
every time drv_rx_start was called. However, that also seems wrong for
a ring buffer. So I am freeing the finished buffers instead.
- Tested on Beagleconnect Freedom.
- Fixes https://github.com/zephyrproject-rtos/zephyr/issues/71191
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
This commit should deal with adding support
for asynchronous operations. It also adds
support for DMA acceleration via a Kconfig
variable (enaled by default as DMA should
be considered scales faster than the
interrupt-driven approach).
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Convert SSD16XX display driver to use MIPI DBI API. This commit also
updates in tree board devicetrees to include the emulated MIPI DBI SPI
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
1. Add a property for panels where the RGB is displayed as BGR.
2. Add a check for 8080 8-bit mode and invert RGB and BGR for
this case.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
udc_mcux_ehci is based on the MCUX USB controller driver
(usb_device_ehci.c); udc_mcux_ip3511 is based on the
MCUX USB controller driver (usb_device_lpcip3511.c);
add related Kconfig and CMake; include the usb_phy.h path in
modules/hal_nxp/usb/CMakeLists.txt because udc_mcux.c use it;
add related macros to usb_device_config.h;
update CMakeLists for udc_mcux_ehci and udc_mcux_ip3511.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
The uart-controller devicetree binding declares current-speed and
data-bits properties as optional, but the max32 uart driver failed to
build if they weren't defined. Fix the driver by falling back to
commonly used values for these properties.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Move it out of boot section because it's also called by none-boot function
'loapic_resume()' at runtime. Better to keep boot-only things in boot
section to avoid paging in boot section things at runtime.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Add Kconfig.nxp to support NXP Bluetooth Chipset.
Current only NXP IW612 Chipset (BT_NXP_NW612) has
been supported.
Add modules/hal_nxp/bt_controller/CMakeLists.txt to
determine whether any firmware is selected, and
check whether the firmware exists.
If the firmware exists, copy the firmware to the
temporary folder ${ZEPHYR_BINARY_DIR}/include/
generated/bt_nxp_ctlr_fw.h. OR, raise a fatal error.
In file hci_nxp_setup.c, includes the temporary file
bt_nxp_ctlr_fw.h.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Implement UART firmware download driver for NXP
BT module.
Only support Murata 2EL M.2 module on RT1170EVKB.
And only one instance can be supported now.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Add conditions to enable ptp_clock driver implementation
for native_posix when PTP subsystem is enabled.
Signed-off-by: Adam Wojasinski <awojasinski@baylibre.com>
Add handling of net_pkt flags that can be used to indicate that the
network packet should be timestamped.
Signed-off-by: Adam Wojasinski <awojasinski@baylibre.com>
Refactor the `QSPI_CommandTypeDef cmd_write_en` definition to
a `static const` local variable to eliminate redundant definitions.
This change enhances performance by reducing runtime overhead associated
with initializing `cmd_write_en` in multiple functions.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add support for display_read API with ili9xxx controller. This
functionality is opt-in, since the required bitshifting makes the
read not very performant, and the implementation adds otherwise unused
code overhead.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert ST7789V display driver to use MIPI DBI API. This commit also
updates in tree boards to use the new devicetree syntax needed to enable
this display with the MIPI DBI API.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is part of a series to move memory management functions
away from the z_ namespace and into its own namespace. Also
make documentation available via doxygen.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This renames z_phys_map() and z_phys_unmap() to
k_mem_map_phys_bare() and k_mem_unmap_phys_bare()
respectively. This is part of the series to move memory
management functions away from the z_ namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
I/O Devices were meant to be handles of sorts and had a built in mpsc queue
as this made sense initially. As time has gone on it turned out that often
we wanted the mpsc queue to be an implementation detail hidden in a driver.
In fact pretty much all drivers work this way now.
Keeping the struct mpsc queue as a member of rtio_iodev meant wasted memory
in cases where it wasn't used. It also meant a bit of confusion as the
queue might be accidently used in places where it shouldn't be.
Remove the mpsc queue member from struct rtio_iodev and the last remaining
usages of it. Will ensure RTIO for 3.7 LTS avoids causing unneeded churn
for future users.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add Kconfig option for enabling high speed USB support for the native posix
USB controller driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Currently, the ram_console buffer is defined as a global var, its
address is determined during the building and may be changed when
code update. This is not a problem if the ram_console is just used
in debug purpose.
While in the heterogeneous SoCs, there can be multiple MPU Cores
and several MCU cores, it can run multiple OS/bare-metal instances
on these cores, but the UART ports may be not enough, so the
ram_console can be leveraged. To make it easy to use, it's better
make the console buffer fixed and predefined.
This patch adds a option to link the console buffer to a given
section, through the "zephyr,memory-region" device tree node, then
the address can be known from the device tree node and easy to
check from other cores running Linux/U-Boot.
To use this option, the chosen property 'zephyr,ram-console' must
be added, the following is a example:
chosen {
zephyr,ram-console = &ram_console;
};
ram_console: memory@93d00000 {
compatible = "zephyr,memory-region";
reg = <0x93d00000 DT_SIZE_K(4)>;
zephyr,memory-region = "RAM_CONSOLE";
};
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add the commands to read and write to/from the xSPI with gpDMA
On the stm32h5 device, the one request for xspi instance
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure the xspi clocks domain by the clock domain
as defined by the DTS
Up to 3 possible clock confg : xspix, xspi_ker, xspi_mgr
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds support for configuring SPI frequency per transaction.
The "clock-frequency" devicetree property is used as the default
frequency unless the peripheral being communicated with has a lower
"max-spi-frequency" (passed to the driver as spi_config::frequency).
An error is returned if the requested frequency is higher than the
hardware can support. This limit is half the peripheral clock (PCLK on
Series 2, HFPERCLK on Series 0/1) for SPI in controller mode.
Previously, the driver hard-coded 1 MHz operation. For backwards
compatibility, default to 1 MHz if the "clock-frequency" property is not
set in devicetree.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit adds support for devices such as EFR32xG24 in the SPI
driver, as these devices only have a single USART peripheral.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
