This commit introduces support for the I3C driver on STM32, enabling
functionality APIs for I3C controllers.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Add set_ctrl function API for vertical and horizontal flip control
modifying the camera read mode
Signed-off-by: Jeronimo Agullo <jeronimoagullo97@gmail.com>
Raise the poll signal when the socket is being closed to prevent users
of `zsock_poll` blocking after the socket is no more.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add cancel action wait ops to cancel remain on channel after TX on
specific channel, in case we need to remain on another channel later.
Signed-off-by: Fengming Ye <frank.ye@nxp.com>
LJ packages have 16 ADC channels vs 8 for SZ packages. Enhance
devicetree to account for this as well as conditional defines/code.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
This patch refactors the power management initialization for the Intel
ADSP GPDMA driver. The changes include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the `intel_adsp_gpdma_init`
function.
2. Ensuring that the GPDMA driver is initialized with the appropriate
power management state and that runtime power management is
automatically enabled based on the device tree configuration.
These changes streamline the power management initialization process and
ensure consistency with other drivers.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch refactors the power management initialization for the SSP
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the `ssp_init` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the SSP nodes
in the device tree files for ACE15, ACE20, and ACE30.
3. Moving the power domain assignment for the SSP device in the device
tree. The previous configuration resulted in the device not being under
any power domain and being initialized as always ON.
These changes ensure that the SSP driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch refactors the power management initialization for the DMIC
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the
`dai_dmic_initialize_device` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the DMIC nodes
in the device tree files for ACE15, ACE20, and ACE30.
These changes ensure that the DMIC driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses the issue of invalid initialization sequence and
the use of registers in `dma_config` before the device is fully
initialized in the Intel ADSP HDA DMA driver.
Changes include:
1. Moving the `intel_adsp_hda_channels_init` call to the
`intel_adsp_hda_dma_init` function to ensure that channels are
initialized during device initialization.
2. Removing the redundant call to `intel_adsp_hda_channels_init` from
the `PM_DEVICE_ACTION_RESUME` case in the
`intel_adsp_hda_dma_pm_action` function.
These changes ensure that the device and its channels are properly
initialized before any DMA configuration is performed, preventing access
to hardware registers before the device is ready.
**Note:** This is a proposed solution, and a different approach should
be considered. Currently, we are accessing registers before the device
and power domain are fully powered up. This solution likely works
because the DMA is used to load firmware during the boot process, and
the necessary power domains are already powered up. Further
investigation and a more robust solution are recommended to ensure
proper initialization and power management.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses several issues with the Intel ADSP HDA DMA driver:
1. Refactors the HDA DMA power management initialization. The previous
use of `pm_device_runtime_enable` was incorrect. The updated approach
relies on enabling runtime power management through the device tree
using the `zephyr,pm-device-runtime-auto` property. Additionally, the
patch removes redundant device initialization steps as these are already
handled by `pm_device_driver_init` when the device is under a power
domain.
2. Corrects the power domain assignment for the HDA link. The HDA link
was previously assigned to the io0 power domain based on a
misinterpretation of the documentation. The correct power domain
assignment is now based on updated documentation for LNL, ensuring that
the HDA link is associated with the appropriate power domain.
These changes ensure that the HDA DMA driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the correct power domains are used.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses the following issues with the Intel HDA DAI driver:
1. Adds power management support for the HDA DAI driver by implementing
the `hda_pm_action` function and integrating it with the Zephyr power
management framework.
2. Ensures balanced calls to `pm_device_runtime_get` and
`pm_device_runtime_put` by modifying the `probe` and `remove`
functions to use these power management calls.
3. Ensures that the io0 power domain is active when the HD Audio is in
use by assigning the correct power domain to the HDA DAI devices in
the device tree files for various Intel ADSP platforms (ace15_mtpm,
ace20_lnl, ace30, ace30_ptl).
4. Enables runtime power management for the HDA DAI devices by adding
the `zephyr,pm-device-runtime-auto` property in the device tree.
These changes ensure that the HDA DAI driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the io0 power domain is active when required.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Compilation will fail if multiple models are used at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The lsm6dso driver does not correctly reflect the status of
the node in dt. So the driver didn't compile even if
`st,lsm6dso32` node exists.
I fixed it to correctly go through ithe compile.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Use the mipi_dbi_configure_te API within the st7796s display driver.
If the MIPI DBI controller supports the tearing enable signal, then
configure the ST7796S to output the TE line signal.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for the mipi_dbi_configure_te API within the NXP LCDIC
peripheral. Also, remove a redundant code patch in the write_command
function that was previously used to determine when the display driver
was writing to graphics RAM, as these writes should now be performed
using the mipi_dbi_write_display API.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename "nxp,kinetis-lpuart" compatible to "nxp,lpuart" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce new binding "st,stm32u5-otghs-phy" for OTG_HS PHY. This allows to
configure clock source and handle STM32U5 specific OTG_HS PHY behavior in
driver implementation in a more readable way.
Move OTG_HS PHY clock selection (previously <&rcc STM32_SRC_HSI48
ICKLK_SEL(0)>) from OTG_HS node to OTG_HS PHY node.
Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5
CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
Support enabling OTG_HS PHY clock, which is bit 15 (OTGHSPHYEN) in
RCC_AHB2ENR1. Change OTG_HS clock to be bit 14 (OTGEN).
Calculate in runtime OTG_HS PHY clock source frequency. Try to match that
to supported (16, 19.2, 20, 24, 26, 32 MHz) frequencies and select proper
option with HAL_SYSCFG_SetOTGPHYReferenceClockSelection() API (instead of
hardcoded 16 MHz selection).
Co-authored-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Support specifying divided clock buses by introduction of
STM32_CLOCK_DIV(div) macro. This macro can be used in devicetree to define
clock source of peripherals.
HSE is selected in devicetree using:
<&rcc STM32_SRC_HSE ...>;
HSE/2 can now be selected with:
<&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
This allows to use clock_control_get_rate() API in peripherals in order to
get desired clock rate.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
in the switch case in the preceeding for loop if default path is taken
all the time, then the ret variable will stay uninitialized, the original
contributor of this driver has provided a comment that this path shall
never be reached, however, it is better to return an error code instead
of continuing with an incorrect configuration, hence this commit replaces
continue with a proper return errno.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
for the brevity renaming direction_gpios to dir_gpios since STEP/DIR
interface is quite an established term in context of stepper controllers.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The current implementation of tmc2209 driver does not allow instantiation
of the driver without configuring msx pins.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The SD physical layer specification requires that the operating supply
be stable for at least 1 millisecond before providing the required 74
clocks. The maximum VDD ramp time is specified at 35ms, giving a total
minimum delay of 36ms.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This PR fixes a blocking call to video_buffer_alloc in case of memory
shortage by addign a timeout parameter to the API.
Signed-off-by: Armin Kessler <ake@espros.com>
Added support for SPI in 4-wire and 3-wire configurations to
the Infineon AIROC WiFi driver (drivers/wifi/infineon).
Review changes:
Move DT_DRV_COMPAT to common header file
Correct board-specific preprocessor lines
Removed AIROC_MAP_COUNTRY_CODE
Move Pico W configuration details to devicetree
Use pinctrl to manage shared data/interrupt GPIO
Clean up bus selection in Kconfig.airoc
Make SDIO and SPI bus struct independent
Replace LOG_DBG with LOG_ERR
Remove functionally duplicate operation
Remove spurious Kconfig option
Minor cleanup in CMakeLists.txt
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
This PR adds support for LAN9250 spi ethernet controller.
This driver is tested on the Mikroe ETH Click 3
https://www.mikroe.com/eth-3-click
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add support for optimized short log messages (aka turbo logs). They are
supported on cpuapp and co-processors owned by cpuapp (FLPR and PPR).
In general, it can be supported if cpuapp has access to logging strings
used for the log message. Currently mode is supported only in standalone
logging. When it is extended for dictionary logging then it will also
be supported on other cores (e.g. cpurad).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
entropy_nrf5 modules uses k_sem_xxx() functions in several
places, but these functions are only functional when
CONFIG_MULTITHREADING is set, otherwise they just fallback to
the empty weak implementation provided in
zephyr/lib/libc/armstdc/src/threading_weak.c.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
mcux_rnga driver calls k_cycle_get_32() which is not available
if CONFIG_SYS_CLOCK_EXISTS is not defined. Therefore we add
this depedendency to CONFIG_ENTROPY_MCUX_RNGA.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Automatically enable ENTROPY_GENERATOR if the device-tree has
any "zephyr,entropy" chosen property specified. This helps
in having CONFIG_ENTROPY_HAS_DRIVER set if the platform support
an entropy driver and this then enables CONFIG_CSPRNG_ENABLED.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Now that we enable `HAS_BT_CTLR` we should also declare which optional
features are supported. For now, we only add the features that are
available through the current driver init routine and found on all
supported platforms.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The tcpc_get_status_register function was using int32_t for the status
parameter, while the other related functions used uint32_t. This change
unifies the data type across all related functions to uint32_t for
consistency and clarity.
Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
When fast UARTE instance is used (e.g. UARTE120 in nrf54h20), PM actions
are not ISR safe because they include communication over IPC so they can
only be called from the thread context. Extend driver to support both
PM modes. When non ISR mode is used then uart_rx_enable() and uart_tx()
will return error if they are called from ISR and resume operation
would need to be called because device is suspended. On completion,
driver is calling pm_device_runtime_put_async which can be called from
the ISR context.
Additionally, suspending in the TXSTOPPED and RXTO events has been
moved after user callback. It allows to support the case where
uart_rx_enable() or uart_tx() are called from that callback context.
Since suspending is called after returning from the callback it will
not trigger suspend action because API called in the callback context
will increment the usage counter (when pm_device_runtime_get() is
called).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Extends the MIPI DBI SPI driver class for operating mode C4, SPI 4-wire,
with 16 write clocks to send one or multiple byte for commands. Generic
data (e.g. GRAM) aligned to 16-bit are passed through and stuffed with
bytes if required.
Signed-off-by: Stephan Linz <linz@li-pro.net>
The more complex the SPI transfer algorithms become, the more
confusing the current implementation of the SPI write function
becomes. Furthermore, if further as yet unknown MIPI DBI modes
are to be supported, the scope of this implementation would
increase dramatically. With the splitting now introduced, the
existing SPI transfer algorithms are moved to individual
auxiliary functions and the SPI write function only focus on
the decision of the respective MIPI DBI mode and the device
lock/unlock.
Signed-off-by: Stephan Linz <linz@li-pro.net>
The more complex the SPI transfer algorithms become, the more
confusing the current implementation of the SPI command read
function becomes. Furthermore, if further as yet unknown MIPI
DBI modes are to be supported, the scope of this implementation
would increase dramatically. With the splitting now introduced,
the existing SPI transfer algorithms are moved to individual
auxiliary functions and the SPI read function only focus on
the decision of the respective MIPI DBI mode and the device
lock/unlock.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Implement the readout protection for the STM32H7 series.
Define the specific functions used by the flash_stm32h7.
Move the stm32h7 flash register manipulation in a write_optb()
to be called by the flash_stm32_set_rdp_level.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
