Use the clock control API to enable the peripheral clock instead of
relying on LL_UCPD_Init().
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The lfclk_spinwait implementation is partially based on
k_cpu_atomic_idle() to idle the CPU while waiting for LFCLK events
if in ISR or in pre kernel. This implementation is fragile and
complex given k_cpu_atomic_idle() is a nop if in ISR, reducing it to
a polling check, and that IRQs are masked globally in pre kernel which
conflicts with the expected use of k_cpu_atomic_idle(), signified by
the need for manually calling NVIC_ClearPending().
This commit refactors the code to use a polling check, sleeping if
possible between checks. This simplifies the wait, without loosing
support for no multithreading since k_msleep() is available even
without threads.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Currently, restrict_tx_outside_tsp is false by default, and with that,
the NWP may transmit data during TWT sleep time. Many APs do not support
this also should not be the default behavior.
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Add support for the ESP32-H2 SuperMini development board, a compact
board based on the ESP32-H2 RISC-V SoC with Thread/Zigbee and
Bluetooth 5 (LE) connectivity.
Signed-off-by: Ivan Shautsou <vano1002@gmail.com>
Ramdisk access fails with data abort when MMU is enabled, due to
using a physical address for the buffer instead of a mapped virtual
address.
Add support for MMU configurations by mapping the ramdisk
buffer to a virtual address space and storing this pointer in
the device's private data (`struct ram_disk_data`). Update all accesses
to use this virtual address when MMU is enabled.
With MMU disabled, the ramdisk continues to use
the original physical addressing as before.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
Refactored RAM disk device instantiation to use a ram_disk_data struct
as the device data, instead of assigning disk_info directly.
This change was made to enable adding additional device-specific data
in the future, improving flexibility for RAM disk devices.
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
In the SL_WIFI_SCAN_TYPE_ADV_SCAN path, the Kconfigs
ADV_ACTIVE_SCAN_DURATION / ADV_PASSIVE_SCAN_DURATION were used only as
a fallback when the per-call wifi_scan_params dwell fields were 0, so
any non-zero per-call value would override them and reach the radio.
BG-scan dwell is a system-tuned policy controlled by Kconfig (like
trigger_level and enable_multi_probe); per-call dwell fields belong to
the foreground scan path only. Always use the Kconfig values for
advanced_scan_config and ignore per-call params on this path.
Signed-off-by: Tejus Subramanya <ters@silabs.com>
This patch adds PM device support to the siwx91x ADC driver. It allows
the ADC to be reconfigured after waking from deep sleep. Without this
patch, the ADC peripheral fails to return valid values after the system
resumes from deep sleep.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Convert the driver clock accesses to use the new generic API, so the
driver can be used on R-Car boards generations 3, 4 and 5 without changes.
Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
Modernize the way the peripheral registers are accessed.
This allows the driver to work on platforms that use a MMU or MPU.
Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
The multifunctional interface (MFIS) provides an interface
between the different CPU core domains (AP/RT, AP/SCP and
RT/SCP).
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Extract the filter handle initialization into a macro to limit nesting/
indentation in the DMIC_DFSDM_FILTERS_DEFINE macro.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Reject invalid requested L/R pairings in the channel map with -EINVAL
before applying hardware limits.
Regular mode supports one DFSDM channel per filter, so configure only the
first requested channel and report that single channel through the act_*
fields instead of failing multi-channel requests outright.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Call HAL_DFSDM_ChannelDeInit() and HAL_DFSDM_FilterDeInit() when
configure() is invoked on an already configured device. Without this,
a second configure() fails because the HAL channel is still registered.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
dmic_trigger(DMIC_TRIGGER_START) returned success while the device was
still in DMIC_STATE_INITIALIZED. Require DMIC_STATE_CONFIGURED and
propagate errors from dmic_stm32_dfsdm_start().
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
A capture cycle (configure -> START -> read -> STOP) without a following
RELEASE leaked memory slab blocks: dmic_stm32_dfsdm_stop() tore down the
HAL but never freed the in-flight buffer the driver still owns, and the
completed buffers sitting in the RX queue were never reclaimed. Each
stop/start cycle therefore leaked at least one block, and with a small
slab the next start's k_mem_slab_alloc() eventually failed with -ENOMEM,
surfaced to the caller as -EIO by the START trigger.
Free the in-flight buffer once conversions and their IRQs are stopped,
purge any completed-but-unread buffers from the RX queue on a fresh
start, and drop both on the deinit path so a stream can be stopped and
restarted indefinitely.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Hard-code RegularParam.Trigger to DFSDM_FILTER_SW_TRIGGER in the static
filter initializer. The previous DT_PROP(flt, filter0_sync) value was a
misuse of that binding property: filter0-sync describes an InjectedParam
synchronisation mode and is only valid on filter instances 1-3. On
filter@0 it expanded to 0 (the same value as DFSDM_FILTER_SW_TRIGGER) only
by coincidence; on a hypothetical filter@1+ with filter0-sync set it would
silently turn regular conversions into a sync-trigger. Use the literal
that matches what the driver actually does (software-triggered regular
conversions) and leave the DT property where it belongs, on InjectedParam.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
HAL_DFSDM_ChannelInit() writes (Awd.Oversampling - 1) into the
CHAWSCDR.AWFOSR field and asserts that the ratio is in [1, 32]. The
static channel initializer in DMIC_DFSDM_CHAN_DEFINE() left
.Oversampling = 0, so:
- in debug/asserts-enabled builds the HAL assert fires immediately
from HAL_DFSDM_ChannelInit();
- in release builds CHAWSCDR is programmed with a wrap-around value
instead of a valid analog-watchdog oversampling ratio.
Default the static struct to a complete, valid configuration
(Oversampling = 1, FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER) so the
HAL contract is honoured before any runtime reconfiguration takes
place.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
The channel map PDM index is not the DFSDM DATIN number. Read the
channel from the devicetree child `reg` instead so boards like Nicla
Vision (DATIN2 on pdm0) route the filter correctly. Update the
stm32f769i_disco sample index to match (0 = pdm0 filter).
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Compute the post-filter PCM scaling shift together with the selected OSR,
where the hardware right shift is already known, then apply that shift when
samples are copied into RX buffers.
Store PCM samples with explicit little-endian helpers instead of memcpy()
so the output layout does not depend on host endianness. Clamp samples to
the requested PCM container width before writing them.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
- Adapt to new MCXW7x clock control
- disable HDI pins
- use flw on non secure range
- enable lpuart1 and use it for uart-pipe, bt-c2h-uart and shell-uart
- configure sys clock to 96MHz for core0 and 48MHz for core1
- use PTA18 for LPUART0 RX pin as workaround for board issue
- fix LPTMR clock source to 32K
- place main stack at beginning of the RAM to workaround boot issue
- move shared memory to third bank (instead of the second) - last 8K
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
WiseConnect zeros the BT half of its cached coex performance profile
on every Wi-Fi disconnect, leaving BT out of power save and preventing
the NWP from sleeping after re-association.
Delegate Wi-Fi power-save to siwx91x_nwp_apply_power_profile(), which
already owns both BT and Wi-Fi halves of the coex profile. Extend the
helper to accept an optional sl_wifi_performance_profile_v2_t override
so the Wi-Fi driver can pass its tailored profile (listen_interval,
dtim_aligned_type, monitor_interval); BT-only and init call sites pass
NULL to keep their current behaviour.
Signed-off-by: Tejus Subramanya <ters@silabs.com>
crc16_reflect() and crc16_ansi() pass a CRC16 context with the
reflected polynomial 0xA001 and both reflect flags set. The driver
only accepted the normal-form 0x8005 and rejected 0xA001 with -EINVAL,
so those helpers returned 0 and the subsys.crc Ztest suite failed on
NXP parts such as frdm_mcxn947.
The CRC engine takes the polynomial in normal (MSBit-first) form and
reflects via reflectIn/reflectOut, so 0xA001 and 0x8005 describe the
same CRC-16. Accept 0xA001 only when both reflect flags are set and
always program 0x8005; a non-reflected 0xA001 is still rejected.
Tested with tests/subsys/crc on frdm_mcxn947: pass = 14, fail = 0.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Per the SX1261/2 datasheet (13.1.12) 0x000000 selects Rx Single mode
and 0xFFFFFF Rx Continuous mode; the two defines had their values
swapped.
No functional change: SX126X_RX_TIMEOUT_SINGLE (0xFFFFFF) was never
referenced, and the continuous receive paths (lora_recv_async, and
lora_recv with K_FOREVER) re-arm RX after every packet in
sx126x_rx_restart(), so they kept receiving even with the chip wrongly
in single mode. The blocking recv path needs only one packet and
sleeps the radio in the RxDone handler regardless. After the swap
those paths use true Rx Continuous mode, with identical observable
behavior.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
GPR bit 0 is Write-Only (WO per DM9051A spec), reading returns
undefined values (default XXh). The previous code read GPR and only
powered on the PHY if bit 0 was set to 1. If the read returned 0x00
(random undefined value), the PHY would never be powered on.
Fix by unconditionally writing GPR = 0x00 to power up the PHY,
ensuring it is always enabled regardless of any prior state.
Signed-off-by: Ching Ping Sun <tom_sun@davicom.com.tw>
Add code comments to make sure the common data/config fields stay in the
correct place in the driver-specific struct if those structs ever get
modified.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
There's no point in having driver specific data structs if the only thing
they contain is the common data struct. Just declare the common data struct
directly as dev->data.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Now that we have a common data struct, we can take advantage of it and
move the recv callback into it. This way the common layer takes care of
assigning, dispatching and clearing the callback. Drivers now have to use
the new bt_hci_recv() API to pass data to the layer above them (typically
a host stack). Additionally, the drivers no longer get a recv parameter as
part of their open() callback, since that's all handled by the common
layer.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add a display driver for monochrome and grayscale LED matrices driven by
charlieplexed GPIOs. With N GPIO lines such a matrix can drive up to
N*(N-1) LEDs: each pixel sits between an ordered pair of lines and is lit
by driving one line high and one low while every other line is held at
high impedance. Only one LED is lit at a time; a timer scans the pixels
fast enough for persistence of vision.
The driver implements the display API. It keeps a per-pixel framebuffer
and uses a counter device as the scan time source, lighting the next
pixel on each top-value callback. Grayscale is produced by duty
modulation over a configurable number of sub-frames. To stay portable
across SoCs it drives the matrix purely through the generic GPIO API,
configuring the inactive lines as disconnected to obtain the required
high-impedance state rather than touching the GPIO registers directly.
The GPIO bank, the per-pixel high/low pin-pair map, the scan timer,
refresh rate and grayscale depth are all described in devicetree through
the new charlieplex-led-matrix binding.
Signed-off-by: Tyler Baker <tyler.baker@oss.qualcomm.com>
Assisted-by: Claude Code:claude-opus-4.8
Use min/max DT properties for reset num-resets DT properties to factorize
documentation and build time check of the property values against its
valid range.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use min/max DT properties for ADC nchannels DT properties to factorize
documentation and build time check of the property values against its
valid range.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Place the I2S DMA callbacks and transfer helpers in IRAM and
mask the interrupt status to the relevant TX/RX events, returning
early on spurious interrupts to keep the ISR path coherent.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
ESP32-P4 does not provide soc/rtc_cntl_reg.h. Skip including
it on P4 along with the existing skip for C5/C6/H2.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
On SoCs with AXI GDMA, derive the DMA slot from the trigger
peripheral ID base. Flush the tx buffer and invalidate the rx
buffer around the transfer so CPU and DMA see coherent data.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Flush tx and invalidate rx DMA buffers around UART async DMA
transfers so the CPU and DMA engine see coherent data on SoCs
with an L1 data cache.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Wire ESP32-P4 specific IOMUX paths and status register layout,
use the combined raw interrupt status field, and align the DMA
descriptors to the cache line for coherent flush and invalidate.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Scale the RNG APB-cycle wait based on the CPU frequency on
ESP32-P4. The RNG has been characterised at around 75 kHz
on P4 ECO5+ silicon.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Explicitly enable the timer clock source via esp_clk_tree
before programming the counter. Required on P4 where the
source clock is gated by default.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Invalidate the DMA buffer after a DMA transfer so the CPU
reads the freshly captured samples instead of stale cache
lines.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add SOC_SERIES_ESP32P4 to the dependency list of the Espressif
systimer driver so it is selected by default and provides the
sys_clock_elapsed implementation the kernel needs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add ESP32-P4 to the Espressif UART driver and the USB-serial-JTAG
backend, including the SoC-specific clock source selection
for the P4 UART HAL.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
