Changes introduced in 293b9a16ca didn't
verify correct behaviour when running `TIMER1` with `TIMER0` is paused,
and was reporting the wrong tick counter being incremented. Correct this
and extend the testing to verify correct behaviour.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add the possibility to activate the XBARB driver
Update NXP HAL revision to include support for xbarb
Signed-off-by: Mathias Landolt <mathias.landolt@loepfe.com>
Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
TI OMAP mailbox is the inter-processor mailbox IP found in TI
K3 devices (AM62X, AM64X, J721E .etc). The mailbox hardware uses
a queued mailbox interrupt mechanism that provides a communication
channel between processors through a set of registers and their
associated interrupt signals by sending and receiving messages.
The interrupt/bank associated with each processor entity is found
through the usr_id property from device tree.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
The `BT_DRV_RX_STACK_SIZE` config is used by HCI drivers to determine a
suitable stack size for their RX thread. These threads handle the HCI
transport and pass HCI messages to the Bluetooth host via `bt_hci_recv()`.
Previously, the default stack size was 256 bytes, but it seems to be too
small currently.
Measuring the peak stack usage of `bt_hci_recv()` in different scenarios
indicates that the function needs over 300 bytes of stack. Thus, an RX
thread stack size of 512 should cover that and leave some margin.
Signed-off-by: Kalle Kietäväinen <kalle.kietavainen@silabs.com>
The EUSART peripheral must always be enabled in configure(), as
its enable state gets cleared when the state machine is unretained
in deep sleep. The rest of the config registers are retained,
so they can continue to not be repainted on every configure() if
the context is the same as last time.
Remove unnecessary duplicated enable at the end of configure(),
the SPIInit HAL function already performs enable.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Only lookup for i3c devices if I3C=y, fixes a build error:
zephyr/drivers/i2c/i2c_shell.c:
In function 'device_is_i2c':
zephyr/drivers/i2c/i2c_shell.c:341:43:
error: array type has incomplete element type 'struct i3c_driver_api'
341 | return DEVICE_API_IS(i2c, dev) || DEVICE_API_IS(i3c, dev);
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix compiler warning when optional property reset-gpios
is not supplied in the ti,tcan4x5x-compatible device tree
node
Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
Add support for TRNG peripherals that lack interrupt lines in the STM32
entropy driver.
This enables usage of the TRNG of STM32WB05/06/07 SoCs with the driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Allow DSA_TAG_SIZE to be set based on the size determined by Kconfig
and the enabled switch hardware.
This fixes support for the KSZ8863 which also has a tail tag of
one byte.
Signed-off-by: Bas van Loon <s.r.vanloon@ziggo.nl>
Drop few redundant device_is_ready for functions that are only used as
argument to shell_device_filter, as shell_device_filter checks for that
alrady.
Suggested-by: Yishai Jaffe <yishai1999@gmail.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit replaces a bunch of ifdefs and bindings with a single
extensible binding, and makes all standard mtime system timers consistent.
Signed-off-by: Camille BAUD <mail@massdriver.space>
In order to allow a custom disk name same as with the standard
sdmmc driver an additional device-tree property was introduced.
Signed-off-by: Carlo Kirchmeier <carlo.kirchmeier@zuehlke.com>
Split the USART driver into separate implementations for Silabs Series 2
and Series 0/1 boards. This change improves maintainability (especially
with the support of pin-ctrl and clock-ctrl on series 2 boards).
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
DMA transfers are supposed to write to buffer tail. Use the proper
pointer to make multipart DMA transfers actually write the data to the
intended location.
The issue was observed on control write transfers where the OUT Data
Stage was at least 128 bytes (because endpoint 0 transfer width is
limited to 7 bits).
The issue is unlikely to happen on non-control transfers because the
transfer size width is at least 11 bits (at most 19 bits) and packet
size counter is at least 4 bits (at most: 10 bits) which means that
at least 2048 byte transfer spanning at least 15 packets (or at least
524288 byte spanning 1023 packets for 19 bits transfer size counter
and 10 bits packet counter) is required to necessitate multipart DMA.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Prepare buffer to receive SETUP data on OUT endpoint 0 after endpoint
halt. This solves the issue where the device would no longer process any
control transfers after the first failed transfer with too large OUT
Data Stage (when processing failed due to data stage buffer allocation
failure).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The DOEPTSIZ0 XferSize field is 7 bits long, meaning that maximum single
transfer can be 127 bytes long. Configure the control write (OUT)
transfers considering the XferSize field size to support transfers with
data stage larger than 127 bytes.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Since some platforms may have some lpuart that are wrapped in lpflexcomm
and some that are not, then change the init code to determine how to
connect the interrupt on an instance basis.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Determine if lpflexcomm wrapped lpi2c by instance and connect
irq differently dependending on that to support platforms with
both flexcomm wrapped and unwrapped lpi2c's.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Determine proper irq setup depending whether the spi is wrapped in an
lpflexcomm or not on an instance basis since some platforms have some
wrapped and some not.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support HyperFlash memory devices on a NXP S32 QSPI bus.
This driver uses a fixed LUT configuration that defined in HAL RTD
HyperFlash driver.
Driver allows to read, write and erase HyperFlash devices.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Create common source code to use for supporting HyperFlash.
Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to
'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig.
Add the 'max-program-buffer-size' property to use for
setting memory pageSize, instead of using
'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting.
Add the 'write-block-size' propertyto use for setting
the number of bytes used in write operations, it also
uses to instead of the 'memory-alignment' property.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Following the commit f98fde07b3, DT_REG_ADDR now expands with a 'U'
suffix as an unsigned value. However, for compatibility with IS_EQ,
a raw value without any suffix is required. Therefore, this update is
necessary.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
The TMP435 is a remote temperature sensor monitor
with a built-in local temperature sensor.
Signed-off-by: Jaakko Rautiainen <jaakko.rautiainen@bittium.com>
Set ctrl9_xl.device_conf bit to 1 in ism330dhcx_init_chip()
prior to start device configuration, as stated in paragraph
9.20 of the datasheet.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
SMI bus error check mechanism is preventing the host SMI bus to be
interferred by noise on board level. Current implementation is checking
if data which is writing to/reading from the PHY has correct CRC sum.
If not, then writing/rading process is repeated by the number of
attempts defined in the KConfig. If repeating transmission will fail
by the numbers of ettemps defined in KConfing, drivers returns an
error.
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
For GIC multiple views feature support, all GIC Re-distributor's
GICR_TYPER.last will be set. Because configuration view-0 can
assign non-contiguous CPUs to views other than 0, in this case
the GIC Redistributors' registers won't seem contiguous.
So the GIC driver should cope with multiple sets of redistributors
like multi-chip scenarios. In this patch we add multiple GIC
redistributor regions support in GIC redistributor iteration.
For more information, refer to the Multi view subsection
in the GIC Technical Reference Manual.
For example:
https://developer.arm.com/documentation/101516/0400/Operation-of-GIC-700/Multi-view
Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Certain HCI events, like advertising reports, are of less importance than
others. This takes the discardable buffer pool into use for such events.
When the system is flooded with advertising reports, discarding some of
them ensures that the system can still handle other events.
Signed-off-by: Kalle Kietäväinen <kalle.kietavainen@silabs.com>
The BT Link Layer needs to get runtime in a timely manner to keep
connections alive and handle other time-critical tasks. This is achieved by
adding a separate thread for it with a meta-IRQ priority, which means it
can preempt other threads. The driver also has an RX thread that passes HCI
messages from the controller to the host stack. This can be a lower
priority cooperative thread, as it doesn't have strict timing requirements.
Signed-off-by: Kalle Kietäväinen <kalle.kietavainen@silabs.com>
When using asynchronous API, transfer will fail if the source buffer is
located in a region that cannot be accessed by DMA. This could happen
when a buffer is declared const, and placed in flash memory, for
example.
Workaround this problem by loading the data into a set of temporary
caches before passing them to DMA.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
