Some instances of the FLEXSPI IP permit limiting AHB bus access so that
no memory access requests will straddle a page boundary. Add a property
to manage this setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
is66wvq8m4 PSRAM always requires the address to be left shifted by
5 bits, regardless of which FLEXSPI port it is on. Fix the addressShift
assignment to be unconditional
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The ADDRSHIFT bit simply left shifts the address written to IPCR0[SFAR],
(or the address used for AHB access), by 5 bits before sending it to the
attached memory. This bit does not have an effect on the base address
used to access the flash/psram device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Transactions from RTIO should result in single calls to i2c_transfer.
This corrects the default handler to first count the number of
submissions in the transaction, allocate on the stack, and then copy
over each submission to an equivalent i2c_msg.
It also cleans up the helper functions to be infallible, taking only the
submission and msg to copy to.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
TXRX is meant specifically to handle a full duplex bus like SPI, I2C is
half duplex meaning only read or write can be performed at once.
Drop TXRX as a supported operation code for the default I2C submission
path.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Updated ADXL345 driver with RTIO stream functionality.
Added Trigger intterupt functionality. RTIO stream is using
FIFO threshold.Together with RTIO stream, RTIO async read
is also implemented.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
Implements the SPIO RTIO API. Refactors internal transcive
fucntios to work with both existing SPI API and RTIO functions.
When SPI_RTIO is enabled the spi_transcieve call translates
the request into an RTIO transaction placed in the queue
that device will execute.
Include the latest refacor changes of RTIO.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
Function dma_smartbond_set_channel_status() used incorrect
condition to release state lock.
In initialization function dma_smartbond_init() function
dma_smartbond_set_channel_status() was called for each DMA
channel and tried to release lock that was never taken.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Timer driver using Microchip 32KHz based RTOS timer as the kernel
timer tick. The driver uses one of the 32-bit basic timers to
support the kernel's k_busy_wait API which is passed a wait
count in 1 us units. The 32-bit basic timer is selected by using
device tree chosen rtimer-busy-wait-timer set to the handle
of the desired 32-bit basic timer. If this driver is disabled,
the build system will select the ARM Cortex-M4 SysTick as the
kernel timer tick driver. The user should specify RTOS timer
as kernel tick by adding the compatible properity and setting
the status property to "okay" at the board or application level
device tree. The driver implements two internal API's for use
by the SoC PM. These two API's allow the SoC PM layer to disable
the timer used for k_busy_wait so the PLL can be disabled in
deep sleep. We used a custom API so we can disable this timer
in the deep sleep path when we know k_busy_wait will not be
called by other drivers or applications.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Use DT_*IRQN helper to get the IRQ number on systems with multi-level
interrupt configuration instead of IRQ number on particular interrupt
controller.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Though nRF7000 is a special Scan only chipset, scan only can work with
any nRF70 platforms, no need for this enforcement and we can keep things
flexible.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
The ieee802154_nrf5 supports the IEEE802154_SELECTIVE_TXCHANNEL
Kconfig option and advertises the IEEE802154_HW_SELECTIVE_TXCHANNEL
capability.
The ieee802154_nrf5 driver now allows to schedule timed transmission
requests with selective tx channel, that is set at the latest
possible moment. This improves reception performance when the
timed transmissions are requested.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
The Kconfig `IEEE802154_SELECTIVE_TXCHANNEL` is added along with
the new capability `IEEE802154_HW_SELECTIVE_TXCHANNEL`.
The new capability of the ieee802154 drivers allows to schedule
CSL transmissions as stated in IEEE 802.15.4-2020 chapter 6.12.2.7
CSL over multiple channels. The benefit of the new API is that
additional call to `ieee802154_radio_api::set_channel()` is not
required. The drivers will switch to the new channel as late as
possible for CSL transmissions thus will not interrupt any reception
that might be in progress until the very late moment when the
transmission actually starts.
This improves reception performance when CSL transmissions are used.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Add wsen_hids_2525020210002 driver with
the corrected name and compatibility with
the hal update as well as added new features.
Signed-off-by: Wajdi ELMuhtadi <wajdi.elmuhtadi@we-online.com>
Updated ADXL362 driver with RTIO stream functionality.
RTIO stream is using both FIFO threshold and FIFO full triggers.
Together with RTIO stream, RTIO async read is also implemented.
Signed-off-by: Vladislav Pejic <vladislav.pejic@orioninc.com>
There is an issue where OUT data is not handled correctly when the
toatl length exceeds the MPS. This update fixes the control handling
for the OUT endpoint.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The ready bit is automatically cleared by hardware. When setting other
bits, there is a chance that the ready bit hasn't been cleared yet,
leading to unexpected USB transactions. This commit addresses this
isuue and locks irq for critical section to prevent racing condition.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The IT82xx2 chip has three FIFOs shared across endpoint 1 to 15, and
the FIFO control register is configured based on the active endpoints.
However, there are some issues with FIFO control.
Firstly, when a TRANS_DONE interrupt occurs, the completion of the
transaction should be determined by the ready and enable bits of the
corresponding endpoint. Additionally, only one non-control IN endpoint
can access the IN FIFO at a time. The FIFO control register is selected
before writing data and cleared after the IN transaction is completed.
For OUT endpoints, all endpoint bits must be selected in the OUT FIFO
control register when the endpoint is enabled. This can result in fake
OUT tokens being detected if an interrupt is triggered by another FIFO.
To prevent this, an atomic out_fifo_state variable has been introduced
to handle the detection of fake OUT tokens.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add support for Bosch bmp390 sensor, the drop in replacement for the
bmp388 with same register but different chip-id. This patch make use
of "bosch_bmp390" or "bosch_bmp388" and set the specific chip-id in a
data->chip-id variable, which then used to check against the register
value.
Additional, manual shift operation had been replaced with ENDIAN safe
macros and calibration values with target variable of int16_t add a
cast for it.
bmp388_spi: read register implementation wrong, fixed it.
tx-buffer must be <addr><dummy><dummy> in order to receive the
register value. Read registers in burst mode and have rx and tx
buffer same spi_buf to avoid clock stop and delay with nrf5.
Signed-off-by: Chris Ruehl <chris@gtsys.com.hk>
The NTC thermistor implementation assumes a constant pull-up voltage
and that the ADC channel is measured against a reference voltage so that
the absolute voltage across the NTC can be calculated. Based on the
relationship of `pullup-uv` and this absolute NTC voltage, the resistance
of the NTC is calculated.
There are applications where the "pullup-uv" is not constant, but VDD.
Most ADCs support relative measurements against VDD. If `pullup-uv` is not
defined, the implementation assumes now that the ADC channel is configured
to use VDD as a reference and therefore no millivolt conversion is
required.
Signed-off-by: Stefan Schwendeler <Stefan.Schwendeler@husqvarnagroup.com>
There were some copy and paste errors that were easily missed where the
wrong print out would happen of an argument with `info` and an extra
autocompelete would happen with the `speed` command.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Fix couple of bugs in exit path:
- In case of calloc failure, return's without unlocking
- memory is freed outside lock, in case of a tiny window of race, this
can cause a crash when this function is called from two threads.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
During Wi-Fi connection UMAC sends an unsolicited regulatory change
event but the driver code always assumes that this event is solicited
hence doesn't free the memory for the event.
Fix this by dropping the unsolicited event as it's not supported yet.
Fixes#79733.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Use int instead of ssize_t for select_get().
This eliminates the unnecessary need for POSIX types.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Add lock to fix race when uart_rx_disable is interrupted by RXTO
event which lead to driver state corruption.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
On uart120 BAUDRATE register is not retained when ENABLE=0 and
because of that BAUDRATE must be set after enabling. Add workaround
to the driver.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add configurable magic byte instead of fixed 0xAA. In some cases, it
is known that certain bytes are less likely in the transmission and
picking specific magic byte may reduce probability of failure of
detection of the correct amount of flushed data.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support for DMM which manages cache and dedicated memory spaces.
Added support for data cache for buffers which are not DMM managed.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
