Even though the STM32 TRNG hardware produces 2- or 4-byte sized words of
random data before triggering an interrupt, the driver currently discards
all but the bottom byte: 50/75% of the produced entropy goes to waste!
Make sure we consume all the random data from each word we read to improve
the entropy generation rate seen by users of the driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The Alternate Function IO (AFIO) block must have the clock enabled
before configuring. Some remappings seem to work without, but some
like EXTI do not. Fix.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Intial serial driver support for RX MCU, this driver utilize
the SCI HWIP for uart communication
Current support include polling API and Interrupt driven API,
some of the code is using Renesas RX Driver Package (RDP) as
hal layer
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Sang Tran <sang.tran.jc@renesas.com>
Initial commit for GPIO driver support on board using RX130 MCUs
* drivers: GPIO: implementation for GPIO driver on RSK_RX130_512KB
* dts: rx: add device node for GPIO of RSK_RX130_512KB
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Intial support of pinctrl driver for Renesas RX MCU
family.
This support base on using Renesas RX driver package in
hal_renesas layer
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
for high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
Initial support of clock control driver for RX MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
Converted ENET_Ptp1588Configure to ENET_Ptp1588StartTimer during reset.
This is to avoid configuring IRQ handlers again in hal driver with
ENET_Ptp1588Configure.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The rate adjustment should be based on nomianl frequency, but not
current frequency. Then any PTP stack with PID control could adjust
frequency well.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The enet handle in mac driver was not shared with ptp driver
properly. This was causing wrong TX timestamp.
This patch is to fix it.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Allow reading the offset register.
This allows reading the offset before setting it if offset is set more than
once.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Don't automatically disable all GPIO ports just because
`PM_DEVICE_RUNTIME` is enabled. Require the user to explicitly call
`pm_device_runtime_enable` on the port, or add
`zephyr,pm-device-runtime-auto` to the devicetree node.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Since the Dual Mode feature doesn't actually work when selected,
and we also realize that we can't support key features of dual
mode, such as bank swap using hardware.
As a solution, we desire to remove this Dual mode feature.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Add driver capability to properly set high performance mode
while setting data rate (thru lis2duxxx_mode_set() API)
based on how power-mode is set into DTS: if it is set to
LIS2DUX12_OPER_MODE_HIGH_PERFORMANCE then configure HP mode,
LP/ULP mode otherwise.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Character glitches are observed when entering suspend and standby low
power modes.
To fix it, we make sure the `poll_out` API waits for the character
transfer to complete. This is aligned with the uart driver API
description.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Calling sensor API functions on devices not in `PM_DEVICE_STATE_ACTIVE`
is a violation of the PM API. Adding manual checks inside of drivers
complicates the drivers and increases ROM footprint for no additional
benefit.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Currently, GPIO16/17 are supported for Ethernet phy
clock out, but some boards are also using GPIO0.
This change allows GPIO0 to be configured.
Signed-off-by: Cliff Brake <cbrake@bec-systems.com>
Replace the usage of __HAL_LTDC_RELOAD_CONFIG which is a legacy
API with __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
New property of the st,stm32-xspi-psram compatible gives
the external PSRAM memory in bits.
The property of the st,stm32-xspi compatible gives
the external PSRAM memory base address
Signed-off-by: Francois Ramu <francois.ramu@st.com>
New property of the st,stm32-xspi-nor compatible gives
the external NOR flash in bits.
The property of the st,stm32-xspi compatible gives
the external NOR flash base address
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Align all sensor drivers that are using stmemsc (STdC) HAL i/f
to new APIs of stmemsc v2.9.1.
Requires https://github.com/zephyrproject-rtos/hal_st/pull/25
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Remove XIP dependency for enabling memory mapping for Q/O/XSPI NOR Flash.
It is not necessary and is preventing configuring an external Flash in
memmap mode if there is no internal Flash (like on STM32N6)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Updated airoc_mgmt_connect to be able use security provided
by user (params->security). If it is not passed, we will perform
scan ssid to detect secure type.
- Fix convert_whd_security_to_zephyr() with correct corresponding
whd_security_t to zephyr security type.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
The current shim driver for flash-nxp-s32-qspi returns invalid error
when handling write, erase operations with zero size.
This issue causes the failure of the tests/subsys/settings/fcb/.
Updated to ignore the flash operations with zero size instead of.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
alarm flags only need to be cleared if PORF flag is set; otherwise,
the RTC is already running and alarm flags must not be cleared
Signed-off-by: Vixay Phimmasane <visuphi@gmail.com>
