This introduces the pinmux_dev driver for the Atmel SAM3X.
This driver implements what used to be the pinmux driver API, which
applications could use to modify the function of pins during runtime.
That functionality is now protected under the CONFIG_PINMUX_DEV option,
which should only be set during the early enabling of a new board, as
there is risk of damage to the board when misused.
Change-Id: I3aa00505d2771b53c41fe687c3e5230e804756be
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Setting the direction of a GPIO pin is not the responsibility of the
pinmux "board" initialisation. This should be left for the GPIO
utilising application.
Some macros that were only used when setting the pin direction are
removed.
Change-Id: I5b63d52446a27fe539c89f0639a8dcadf5ea9f80
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This driver doesn't provide any API, it only initializes the pinmux
controller to appropriate values depending on the board.
The first board to use this new infrastructure is the Arduino 101 board,
because it is alphabetically the first.
To better organize code for the different SoCs and boards, a "family"
level is created in the 'drivers/pinmux' directory. The Arduino 101
board is part of the Quark MCU "family".
The PINMUX_DEV configuration (and functionality) is removed for now, it
will be added back when the pinmux_dev drivers are (re)introduced, with
clearer semantics.
Change-Id: Idf5cc3caf6be620aa50828ae8fdc535df6caf458
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
ASSERT are put each time the timer0 limit register or the timer0 count register
is modified.
Change-Id: I38684d57803de285f4e26c68b449c71396e4c750
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
Add device driver for the gyroscope part of LSM9DS0 gyroscope.
Datasheet:
https://www.adafruit.com/datasheets/LSM9DS0.pdf
Change-Id: I25e0c8470c9b68c594bc4a0d2a9a13f8f41ee309
Signed-off-by: Murtaza Alexandru <alexandru.murtaza@intel.com>
When exiting from tickless idle uppon an external IRQ, the TICK timer
is set to fire at next TICK boundary. The current algorithm can lead
to a point that timer0_count register is higher than the timer0_limit
register.
In this situation the next TICK will fire after the counter has
wrapped and performed another cycle (~133 seconds).
This condition appears when the counter reaches the limit after the
Interrupt Pending flag is checked. At this point the counter is
automatically wrapped to 0, but is set just next to the limit to fire
at next TICK boundary by SW. At exit of the _timer_idle_exit function,
the timer handler is called, and sets the limit to 1 TICK. At this
point the situation is:
- limit register == 1 TICK
- count register is just below the old limit register and higher than
1 TICK
To fix this issue, at _timer_idle_exit, the limit register is always
set to 1 TICK and the count register set such as the next TICK fires
on time.
Change-Id: Ifa002809d426aa04109592e53d2b02a224f51101
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
The timer counts from 0 to programmed_limit included.
Change-Id: Ifc8585210c319f5452fafc911d4f6d72c4b91eaa
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
This patch fixes gpio_stm32 driver since it was merged with a few
occurrences of DEV_* error code.
Change-Id: I025e4f83d8ca07bc0fed7d3dcb9cce3b9d11c3fc
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Counter API and drivers were merged without fixing the new returning
error convention (errno.h codes). This patch fixes all occurrences of
DEV_* codes so -E* codes are used instead.
Change-Id: I85007e8565686b52121410badea547ed904460a0
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Moves config options for K64 into its own config file under its
own submenu.
Change-Id: I94ccac54709ab5ec8222daa8634818d9ebc3561d
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Makes K64 spi driver submenu available only if K64 soc is
selected.
Change-Id: I0ada8863a592f056dbe48e78d9374f2348dcac14
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Makes K64 pwm driver submenu available only if K64 soc is
selected.
Change-Id: I9959b4785c6deab01977f86bbbebe3d671a4eec7
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
According to the Core Sepcification, Advertising Interval Min/Max
shall not be set to less than 0x00a0 if ADV_SCAN_IND or ADV_NONCONN_IND
type is used.
Change-Id: I6c4ef4f73b82841c3a96694dda670cdd12a40a54
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Makes K64 gpio driver submenu available only if K64 soc is
selected.
Change-Id: I4097006a4dca718ed2da730fa85cd2ad9970f419
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Moves STM32 gpio driver under its own submenu, like atmel SAM3
and K64 gpio drivers.
Change-Id: Iebc474af9818a73275f99183d3f4788eea1e6ded
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Add support for use of HSE (incorrectly named PREDIV1)as input of PLL,
along with HSE bypass for stabilized external clock, and XTPRE
prescaler. Update PLL handling so that we do not unnecessarily enable
PLL clocks, instead enabling only the clocks sources that are required
as per user's configuration.
This change allows higher SYSCLK clock values, up to 72MHz.
Change-Id: Ia7c2be3ce11ac0de2efa664b20e7ab5fddd57a51
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Move re-enabling logic to the NBLE stack.
Change-Id: I1b895aa952a241dc41e2fc9faa2794a8c2c2d2db
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add driver for the HDC1008 temperature and relative humidity
sensor.
Datasheet:
http://www.ti.com/lit/ds/symlink/hdc1008.pdf
Origin: Original
Change-Id: I63cb4cdd94120b80d0d6f3205da073f0817c4f17
Signed-off-by: Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
This moves both the Bluetooth HCI and NBLE drivers under
"Bluetooth Drivers" category. This also adds a selection for
choosing Bluetooth stacks as the bulk of both HCI and NBLE stacks
cannot be compiled together.
Note that this does not move the source files. That should be
done in a separate change.
Change-Id: I32fa7097ada0fdc52bcc745adb78c7273f4023c6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add device driver for the BMA280 I2C-based triaxial accelerometer
sensor, which supports reading data from the accel-x, accel-y, accel-z
and temperature channels. The driver also has support for data-ready
and any-motion triggers.
Datasheet:
http://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMA280-DS000-11_published.pdf
Origin: Original
Change-Id: Iff7246d7dd4a9358ec7a71e8ffbcfcccd49e393c
Signed-off-by: Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
Signed-off-by: Teodora Baluta <teodora.baluta@intel.com>
This patch fixes the QMSI UART shim driver so we are able to use it in
Quark D2000 based platforms. Differently from Quark SE, the peripheral
clock gate bit (CLK_PERIPH_CLK) is not enabled by default in Quark
D2000. We have to explicitly set this bit in order to properly initialize
the device.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: I817b7703554be162ac628dcd8d3d07512b9eb3f5
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch fixes the gpio, i2c and watchdog shim drivers so they set the
CLK_PERIPH_CLK bit during driver initialization. Differently from Quark
SE, the peripheral clock gate bit (CLK_PERIPH_CLK) is not enabled by
default in Quark D2000. We have to explicitly set this bit in order to
properly initialize the device.
This issue has been masked so far because the CLK_PERIPH_CLK bit is set
when UART NS16550 driver is enabled. The UART NS16550 driver is enabled
by default for Quark D2000 so gpio, i2c and watchdog sample apps were
working just fine. But if we disable the NS16550 driver, these samples
applications stop working.
The remaining shim drivers already set the CLK_PERIPH_CLK bit during
initialization so there is no need to fix them.
Change-Id: I3f658da564f87e9d52092ce7aac423c7b3e0c890
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Add a driver for Independent Watchdog (IWDG) commonly found in STM32
MCUs. The driver has been tested on STM32F1 family MCU.
Change-Id: Idc6ac35990e46901a206b4af0ce3767eb4875de9
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add support for interrupts for input GPIO pins on STM32 MCUs. The SoC
support code is expected to provide an implementation of
stm32_gpio_enable_int() call.
Change-Id: I61bae54b8e044be4d7d8eb60c0c67b71f8c59553
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Introcuce a driver for External Interrupt/Event Controller (EXTI) found
on STM32 MCUs.
Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
The patch extends STM32 serial port driver with support for IRQ API of
the common UART port driver API.
Change-Id: If105e8528ea4ed4181cc4af0c97c24aa874e69e0
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add driver for U(S)ART ports on STM32 MCUs. The driver implements basic
RX/TX functionality. Data transmission is implemented using polling. The
driver configures the port to use 8bit data transmission, 1 stop bit, no
parity control.
The driver exposes a public uart driver API and registers a single UART
device 'UART_0'. The device binds to USART1 peripheral and performs
required pinmux and clock control configuration. The device can be
initialized at the PRIMARY level, with default device priority.
The driver has been verified to work with a sample Hello World
application on a STM32F103 series MCU.
Change-Id: Iae103fcd8d2fb0a6c173cf141a68e17791255aab
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add necessary integration code enabling use of common STM32 pinmux
driver.
The alternate function listing currently consists of USART1 pins
only. The listing should be updated when support for more devices is
added.
Change-Id: Ic65aeea9df9aaea7636ecdd6996f56e6ef59dc2f
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
The driver implements a GPIO device interface for STM32 MCUs. Each SoC
must provide implementation of the follwoing calls:
stm32_gpio_flags_to_conf(), stm32_gpio_configure(),
stm32_gpio_set(). Consult gpio_stm32.h header for details on semantics
of these calls.
The driver registers 5 devices, each corresponding to a single GPIO
port. The users can then access individual pins by using values
0-15.
Change-Id: Id236b5b75c9dd091018a50a7be3501c8591cd551
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add a common driver for pin control subsystem in STM32 MCU series. The
driver allows for selection of pin's function without the ability of pin
remapping.
The driver implements a pinmux driver API, with custom `func` and `pin`
encoding in API calls. The caller is expected to use STM32PIN() helper
macro for encoding port/pin numbers or using one of the provided
STM32_PIN_* defines.
The common driver requires SoC specific support to be implemented. The
SoC code must implement these calls: stm32_get_pin_config(),
stm32_get_port_clock(), stm32_pin_configure(). Consult pinmux_stm32.h
header for detailn on semantics of these calls.
The driver also requires board level integration. The call
stm32_board_get_pinconf() is expected to privide pin function
assignments for the target board.
Whenever an IO pin is being enabled, the driver will automatically
enable the clock for corresponding port. The driver does not implement
disabling of port's clock as this has potentially disruptive, as such
such operation should be done explicitly in the code.
The pin control module needs to be initialized before any other modules,
but after clock_control. For this reason, the driver is initialized by
default at PRIMARY level, with priority set to 2. The priority can be
changed through configuration.
Change-Id: I8cb746d0f3cad72cd50b3355fe6d93a9f469be25
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Current design of Nordic RPC requires strict firmware compatibility,
add check indicating if firmware is incompatible. At the moment we
allow to continue since something may work :).
Change-Id: Ie67d4a6509e53553ae6c41a2c8d2593ab20bdcfb
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Allow to use Non Resolvable Private Address (NRPA) in advertisement,
following NBLE change.
Change-Id: I9491cfcd2e981237c99e55773a8beaddaee8b730
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Update firmware version to 0317. Changes are mostly related to
advertising.
Change-Id: I3a438ad38e3c892e354f7ea59b99739153957f19
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This moves the kconfig options for each drivers into their own
submenus. This makes menuconfig easier to navigate.
Change-Id: I2bdc8c3b61e424248ffb65385a7eabc797d89684
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves the kconfig options for STM32F10X clock control driver
into its own submenu.
Change-Id: I9ef658defe85feab3dfdb3e329710cb48bbffd86
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Moves the Quark SE clock control into its submenu.
() Fixes the dependencies in the SoC default Kconfig
so the options are not displayed out of place in
menuconfig.
Change-Id: Ifdf06242be8ceed03c2c657c942875a5a7f2750e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
