This patch adds adds an EEPROM driver supporting the on-chip EEPROM
found on NXP LPC11U6X MCUs. Note that this driver is only a wrapper
relying entirely on the IAP (In-Application Programming) EEPROM
commands.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This patch adds a pinmux driver allowing to configure the IOCON (I/O
control) registers found on the LPC11U6x MCUs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Flexcomm's SPI SSEL (or CS) will be held until frame end.
FIFOWR[EOT] (kSPI_FrameAssert enum) is the register not set.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Per the nrf9160 datasheet, UARTE must be disabled prior to configuring
PSEL.TXD, PSEL.RXD, PSEL.CTS, and/or PSEL.RTS. This also ensures that
any prior running code, such as a bootloader, which leaves the UART
enabled will not prevent the Zephyr application from changing the
configuration.
Make a similar change also to the uart_nrf_uart.c driver for the
nRF5 series.
Fixes 27080
Signed-off-by: Pete Skeggs <peter.skeggs@nordicsemi.no>
Need to call PINT_Init to initialize the block
before using it. This fixes the issue seen on
RT600 with the button example
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
- Use common clock names to avoid build error.
- Use GPIO_PortInit() to do reset/clock initialization. Only clock
enable is not adequate for RT600.
- Update to support differences between IOCON and IOPCTL modules
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
There are multiple CID errors all based on the test of
'socket > ESWIFI_OFFLOAD_MAX_SOCKETS'. The test needs to
be '>=' in all cases.
Fixes: #27138Fixes: #27139Fixes: #27140Fixes: #27141Fixes: #27142Fixes: #27143
Signed-off-by: David Leach <david.leach@nxp.com>
By fixing the issue: #21819 in the shell, it is no longer needed
to keep a workaround, which allows prompting i2c bus name.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordisemi.no>
When CONFIG_POSIX_API is set in lieu of CONFIG_NET_SOCKETS_POSIX_NAMES,
some macros such as POLLIN, POLLOUT and MSG_PEEK are undefined, and
the appropriate posix headers need to be included to access those.
Signed-off-by: Vincent Wan <vwan@ti.com>
Adds native_posix hw counter model and the counter driver.
Functionality is needed by software which is tested
on native_posix and has dependency on counter.
Hardware model was developed similarly to HW timer model.
The counter driver wraps HW counter functions and exposes
basic functionalities: starting, stopping, setting and cancelling
single channel alarms.
Code was tested against: tests/drivers/counter/counter_basic_api.
Signed-off-by: Filip Zajdel <filip.zajdel@nordicsemi.no>
Add HSE,HSI,CSI,PLL as system clock options.
Also add correct configuration of the PLL.
New sysclk options:
- HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y
- HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y
- CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y
Existing sysclk options:
- PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
PLL clock options:
- More PLL source clocks:
Existing:
1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
New:
2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y
- PLL vco input range is auto-calculated based on PLL DIVM1
-> Example for sysclock 96MHz generated with PLL from HSI
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h
instead to setup the correct latency.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
eSPI slave driver should only indicate that a channel is ready
after the eSPI master has enabled said channel.
However, this indication is incorrectly sent during eSPI reset
even before channel renegotiation starts.
Perform only channel-specific interrupts enabling inside
initialization functions.
Send Channel ready ack only after channel negotiation is received.
Add missing callbacks for channel events to notify client driver.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Update stm32 ethernet driver to get basic boot configuration from
device tree.
So far information are:
- Label
- Base address
- IRQ number and prio
- Clock settings
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add 64bit source_address/dest_address fields support.
This is needed in situation where DMA controller is capable
of handling more than 32bit source and destination addresses.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Fix compilation warnings when CONFIG_NET_SOCKETS_OFFLOAD enabled
warning: passing argument 5 of '__eswifi_socket_new' makes pointer
from integer without a cast [-Wint-conversion]
395 | idx = __eswifi_socket_new(eswifi, family, type, proto, 0x50CE);
| ^~~~~~
| |
| int
eswifi.h:137:21: note: expected 'void *' but argument is of type 'int'
137 | int proto, void *context);
| ~~~~~~^~~~~~~
In function 'eswifi_socket_bind':
warning: comparison between pointer and integer
461 | if ((addrlen == NULL) || (addr == NULL) ||
|
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
use common log module across all eswifi sources, which allows
to compile with CONFIG_NET_SOCKETS_OFFLOAD.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
It is useful to show sensor channels for a battery in cohesive block as
it is easier to read. Add a 'battery' command to handle this. It only
supports a single battery, relying on the device-tree alias to select
it.
uart:~$ battery
Temp: 23.55 C
V: 4.31 V
V-desired: 4.40 V
I: 574 mA (CHG)
I-desired: 2000 mA
Charging: Not Allowed
Charge: 100 %
V-design: 3.86 V
Remaining: 6764 mA
Cap-full: 6764 mA
Design: 6910 mA
Time full: 0h:00
Time empty: 0h:00
Signed-off-by: Simon Glass <sjg@chromium.org>
The EEPROM device doesn't mutate the source data it's given, so update
the API signature to reflect this fact.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
It can happen that the command '>' is received between
modem_cmd_send_nolock and modem_cmd_handler_update_cmds. Since the
command handler for '>' is not set, sem_tx_ready will not be given
and _sock_send will timeout. Make sure the command handlers are set
before the send by also passing them to modem_cmd_send_nolock.
Signed-off-by: Tobias Svehagen <tobias.svehagen@gmail.com>
Add support for the NXP KE1xF SoC to the eDMA driver. The KE1xF supports
m2m DMA transfers from sources 60 to 63.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
add DTCM caching management in KConfig for stm32h7
add NOCACHE_MEMORY support for stm32h7 M7 CPU series
add HAL_RCC_EX support for stm32h7 series
implemented stm32h7 support within stm32 eth driver
Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
added changes that apply to other than stm32h7 series
and prepares stm32h7 series integration:
eth_tx/eth_rx: changed type of total_len
added necessary defines for
tx_desc and own flag extractions
added read_eth_phy_register() function
and corresponding defines
added ETH_DMA_MEM and CACHE defines
following memory buffers declarations moved out of
its ifdef preprocessor macro:
dma_rx_desc_tab, dma_tx_desc_tab,
dma_rx_buffer, dma_tx_buffer
added hal_ret stm32 HAL status checks
Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
Added extra asserts to write function of SDL display driver to check if
write is within bounds.
Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
IPv6 support was not fully implemented in the driver and was disabled.
This commit completes the implementation and enables it when
configured.
Signed-off-by: Vincent Wan <vwan@ti.com>
After switching nSIM to 16550 UART model & driver there is no users
for ARC-NSIM UART. So remove it entirely.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
