We generated a define for each instance to convey its existance of the
form:
#define DT_<COMPAT>_<INSTANCE> 1
However we renamed all other instance defines to be of the form
DT_INST_<INSTANCE>_<FOO>. To make things consistent we now generate a
define of the form:
#define DT_INST_<INSTANCE>_<COMPAT> 1
We also now deprecate the DT_<COMPAT>_<INSTANCE> form and fixup all uses
to use the new form.
Fixes: #17650
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Up to now, the only SOC that was supported in the STM32L496 series was
STM32L496XG with flash of 1MB. With the recent support of STM32L496XE,
this implementation is not correct. This patch adds support for the
other SOCs that come with flashes of 512KB and 256KB.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
Make use of the new flag introduced in nrfx v1.7.2 that suspends
transfers, in order to properly handle scattered I2C transactions,
especially to perform i2c_burst_write() in the way expected by
display drivers, i.e. as a continuous transaction on the bus,
without the repeated START between its two parts.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Implement a CAN shell. With this shell you can send messages,
attach and tetach filters.
Messages that match the attached filters are printed to the shell.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
HSEM_CR_COREID_CURRENT was used as process number parameter in
LL_HSEM_ReleaseLock function. While this is working, this
define should not be used in this context.
Also, process number parameter is actually proposed in case of HSEM
use in inter-process context but is not required for inter-core
resource lock. Replace HSEM_CR_COREID_CURRENT with 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add eSPI Microchip XEC driver
Include support for peripheral & virtual wires (channel 0-1)
OOB and flash support can be added in the future
Fix compilation error in pinmux driver
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Sometimes i2c operation does not return in a while loop.
Fix this by adding timeout to the i2c driver.
Fixes: #12261
Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The previous code limited the length of a write to the size of a page,
but did not check whether the starting position was far enough into the
page that the write would still cross a page boundary.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This was always intended to be a bytestring rather than an array, but
full support was missing. Since that has been addressed switch it to
the preferred format.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The driver historically used the erase block size (64 KiBy) as the page
size. There are other viable "sector" sizes, and for some applications
this one may be too large. Allow the application to specify the desired
flash page size.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The JEDEC API defines the hardware page, sector, and block sizes.
Deprecate the Kconfig settings, remove the `erase-size-block` property,
and add `has-be32k` to indicate that 32K-byte erase is supported.
Rework the driver to use the constants instead of configured values.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The adc_stm32 driver used system timer frequency as a base for
busy-wait delay calculation. This commit corrects that by obtaining
the needed value from SystemCoreClock variable.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The wdog_cmsdk_apb driver used system clock frequency
as a base for timeout calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_cc13xx_cc26xx driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_stellaris driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_qmsi driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_msp432p4xx driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_cc32xx driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_pl011 driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_cmsdk_apb driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The spi_dw driver used system clock frequency
as a base for SPI bus frequency calculation.
This commit corrects that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The clock control initialization code used system clock
frequency as a CPU clock frequency. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The i2c_cc32xx driver used system clock frequency
as a base for I2C clock frequency calculation.
This commit corrects that by obtaining the needed value from DTS.
Please note, that for I2C devices the clock-frequency property
specifies SCK frequency, instead of frequency of the clock driving
peripheral. To solve that problem, a new property was added.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
On some SoCs the frequency of the system clock is obtained at run time
as the exact configuration of the hardware is not known at compile time.
On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define
directly introduces timing errors.
This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call
to inline function sys_clock_hw_cycles_per_sec() which always returns
correct frequency of the system clock.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
On some SoCs the frequency of the system clock is obtained at run time
as the exact configuration of the hardware is not known at compile time.
On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define
directly introduces timing errors.
This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call
to inline function sys_clock_hw_cycles_per_sec() which always returns
correct frequency of the system clock.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
On some SoCs the frequency of the system clock is obtained at run time
as the exact configuration of the hardware is not known at compile time.
On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define
directly introduces timing errors.
This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call to
inline function sys_clock_hw_cycles_per_sec() which always returns
correct frequency of the system clock.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
So far we supported normal (10 bit) and low-power (8 bit) modes. Add
support for high-resolution mode as a third option.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Liteeth exposes two memory regions:
* set of rx/tx buffers (aka slots) to exchange packets,
* control and status registers.
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This patch introduces a dedicated work queue for handling the events
from ISR (i.e. for notifying the USB device stack, for executing the
enpoints callbacks, etc.). The system work queue cannot be used for
this purpose as it might be used in applications for scheduling USB
transfers and this could lead to a deadlock when the USB device stack
would not be notified about certain event because of a system work
queue item waiting for a USB transfer to be finished.
The FIFO named so far `work_queue` is renamed to `usbd_evt_fifo`
to better indicate its purpose and to avoid confusion.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Rename the controller Kconfig option BT_LL_SW to
BT_LL_SW_LEGACY in preparation towards switch to new Link
Layer implementation.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
For STM32F7 MCU the actual implementation doesn't work when the
DMA buffers are placed in the SRAM.
This might be a problem with caches.
To overcome this problem, the buffer is moved to the DTCM.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Flash size calculation was don with assumption that flash page size
is always 1 KB and flash size was parameterized with such granularity.
This patch correct this bug.
Flash pages number under statistic can't be calculated via preprocessor
anymore - thus are parameterized via Kconfig.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
