Add support for the STM32WL integrated radio, based on the sx1262. The
STM32WL implementation does not use any GPIO, and the signals are routed
to other units of the SoC and accessed with the ST HAL.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Convert the standalone part of the sx126x driver to the new gpio_dt_spec
APIs. This allows moving the specific GPIOs in that part of the driver
and out of struct sx126x_data.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This adds support for controlling the SUBGHZSPI NSS line in STM32WL
devices. This is a special dedicated SPI port only connected to the
radio device internally, chip select happens through a bit in the PWR
module. Adding a special dt-property to identify the port, it all gets
built out on non-WL devices.
Deduplicate the existing dts bindings in the process, and add the new
one for the special spi with the new property.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Current impĺementation fails due to missing stop bit
when reading data. This fixes it and refactor the implementation
by adding k_busy_wait when waiting I2C bus completion.
Also, this implementation is based on esp-idf v3.0.
It will be refactored based on latest esp-idf v4.3 using proper
low level calls.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fixes#34015
The STMPE1600 is an I2C based GPIO expander. This initial patch
only supports reading from/writing to the pins on the STMPE1600,
and there is currently no support for interrupts.
Signed-off-by: Titouan Christophe <moiandme@gmail.com>
To be able to get a tokenize DT string without the quotes. Deprecate
also DT_ENUM_TOKEN and DT_ENUM_UPPER_TOKEN.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Fix a couple of issues related to Power Management:
1. A build error because 'dev' was used even if not declared
in the caller routine scope
2. The lis2mdl power management init specific routine was
not declared in in the device instance definition
Signed-off-by: Armando Visconti <armando.visconti@st.com>
So far modem API used UART device names / labels. Change API to operate
on device pointers instead, so that we stop using device_get_binding()
in modem core and in some DT compatible modem drivers.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
When stopping the interface, also abort the RX routine and enable RF
power saving. Will re-start RX on iface start.
Also fixed a bug with `cmd_fs` crashing at RF wakeup because `rf_mode`
was allocated on stack.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
CRC16 was removed by simply decreasing length of the last fragment by 2.
This worked as long as last fragment was longer than 1 byte. If not,
then last fragment was corrupted (its length ended up being 65535),
leading to undefined behavior.
Fix CRC16 removal by utilizing recently introduced
net_pkt_remove_tail(), that properly handles multiple fragments.
Reported-by: Jim Paris <jim@jim.sh>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
If a write offset isn't a multiple of the nor page size, and the
length is too large to fit within a single page, it could wrap around
in that page.
Tested on i.MX RT1064 internal flash using NVS settings
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
replace custom crc8 with sys/crc8
use sys_put/sys_get helpers for byteorder specific operations
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add driver for sensirion consumer humidity sensor line.
Supports shtc1 and shtc3, but only shtc3 is tested.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Instead of waiting forever for the SPI transfer to complete, let's use
a timeout value and bail out if elapsed. The timeout value logic is,
xfer_len/frequency + tolerance
Tolerance value can be modified using a Kconfig symbol,
CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE. It defaults to 200ms.
Fixes: #33192
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Fix macro used in g4 file to enable LSE clock.
Then, to avoid no-op configurations, generate an error
when MSI Hardware auto calibration is selected but LSE
clock is not enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This PR addresses radio signal stength measurement during
and before PPP session. The PR provides provides facility
of readout for both +CSQ and +CESQ versions depending
upon the modems. This PR follows the idea of rssi readout
of PR#35496. Additionally, reliable Cell info update
is also ensured.
Signed-off-by: Tahir Akram <mtahirbutt@hotmail.com>
This patch add support for I2C on the Renesas R-Car.
This I2C hardware block can be found on various Renesas R-Car
SoC series.
It allows to perfom read and write on I2C buses in an
interrupt based way on R-Car Gen3 H3ULCB board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add NXP Kinetis Low Power Timer (LPTMR) OS timer driver shim. Since the
LPTMR does not support asynchronous changes to the timer period, only
non-tickless mode is supported.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The config/data casts are not strictly necessary. Furthermore, config
was being casted to non-const.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use the recently introduced struct gpio_dt_spec to store GPIO
information and operate with them.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This is called in ISR context and timeout must be set
to K_NO_WAIT.
Reported-by: Pieter De Gendt <pieter.degendt@basalte.be>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This commit adds a serial dummy driver compatible to vnd,serial.
This is needed that devices can access the uart device in tests
like tests/drivers/build_all/... .
Add myself as codeowner to avoid complicance check failure.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Use GPIO output high and low to simulate I2C start and stop
conditions to restore i2c to normal.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Create the pinmux phandle to the I2C driver node in the
devicetree. When the pinmux_pin_set function in
i2c_it8xxx2_init can refer to the setting of this phandle.
It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The SoC driver name is 'USB High-Speed Interface (USBHS)'. This rename
from usb_dc_sam to usb_dc_sam_usbhs allowing add others SoC drivers
like 'USB Device Port (UDP)' that is found at SAM4S/E variations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add single-register MMIO GPIO driver for complex cases where
only several fields in register belong to GPIO lines and each GPIO
line owns a field with different length and on/off value.
Such CREG GPIOs are used in Synopsys em_starterkit and HSDK boards.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
This commit add the support of "Interrupt driven UART"
to the R-Car UART driver and enable it in the related
Kconfig.
The driver is supporting nearly all the methods that are
described in the "Interrupt driven UART" part of the
uart_driver_api.
This new version of the driver has been tested on
H3ULCB board by running "uart_basic_api" test suite.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit adds entropy support for stm32wl and stm32g0.
Pll is used as clock source and has to be enabled,
other clock sources are not supported at the moment.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
To support single core stm32wlex series, cpu2 prescaler is set
only on dual core soc variants.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The callback is not used anymore, so just delete it from the pm_control
callback signature.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
the device PM callback is not used anymore by the device PM subsystem,
so remove it from all drivers/tests using it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Armv8-A and Armv8-R both support PSCI. So PM_CPU_OPS_PSCI's
dependency should be "ARM64" rather than "ARMV8-A".
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
There is a name clash when using G4 series LL TIM driver depending on
the inclusion order of the LL TIM and pinmux headers. If the LL headers
are included after pinmux is included, AF1 and AF2 definitions used by
pinmux clash with the AF1 and AF2 TIMx register names.
In order to solve this problem with minimum impact, the following has
been done:
1. Prefix the AFx and ANALOG definitions with STM32
2. In order to avoid changing all *-pinctrl.dtsi files, the STM32_PINMUX
macro contatenates STM32_ with the provided mode.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
refactor flash_page_get_info to simplify and to avoid using mixing the
usage of an off_t (offs) and an uint32_t (page_index).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
In stm32l5xx soc, the LL_DMA_InitTypeDef has 2 more fields
(DoubleBufferMode and TargetMemInDoubleBufferMode) that must be
initialised with 0 else the configuration is wrong and gives
wrong values to the LL_DMA_Init function. Due to this the test
tests/drivers/dma/loop_transfer too would fail.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Fix some leftovers from the pm_device_state changes.
Fixes build problem introduced in
cc2f0e9c08.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This change ensures the CPU won't get an interrupt number which is
being generated.
it8xxx2 has a limitation for interrupt vector register.
CPU may read incorrect interrupt number in ISR.
The following is an example that got incorrect interrupt number:
1. Register IVECT = 0x10. (no interrupt pending/IVECT_OFFSET_WITH_IRQ)
2. Chip INT6 interrupt occurs (IVECT = 0x16) and jump to ISR.
3. Read interrupt vector register to determine interrupt number.
4. Higher priority interrupt occurs (for example: INT158, IVECT = 0xAE)
while the CPU is reading the interrupt vector register for EC INT6,
CPU may end up with an incorrect interrupt number between 0x16 and 0xAE.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
__LL_RCC_CALC_HCLK1_FREQ is only available for WL and WB series,
for other series __LL_RCC_CALC_HCLK_FREQ should be used.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The nRF QSPI has a configurable delay from the rising
clock signal to the actual sample point measured in
clock cycles. This commit exposes that delay as a DTS
parameter without modifying existing behavior.
Signed-off-by: Abram Early <abram.early@gmail.com>
