The FDC2X1X driver depends on newlib in Kconfig. This prevents the
driver from being built in a native_posix testing environment, which uses
an external libc from the host. Allow the driver to be built with an
external libc as well.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
STM32 RTC driver for the new RTC API.
Can't coexist with old COUNTER based RTC
Though supported by HW, RTC_ALARM still to be supported by driver
Signed-off-by: Kim Bøndergaard <kim.bondergaard@prevas.dk>
New RTC API seems to conflict with old RTC implementations based on
COUNTER
This scheme follows Zephyrproject-rtos issue 56599 while keeping backward
compatibility.
Signed-off-by: Kim Bøndergaard <kim.bondergaard@prevas.dk>
The SSP driver depends on DMA as there are references in the devicetree,
but it currently initialize before the DMA driver itself. This is
exposed by the build time priority checking
(CONFIG_CHECK_INIT_PRIORITIES=y) and shows up as:
ERROR: /soc/ssp@77a00 POST_KERNEL 32 < /soc/dma@7c000 POST_KERNEL 40
ERROR: /soc/ssp@77800 POST_KERNEL 32 < /soc/dma@7c000 POST_KERNEL 40
ERROR: /soc/ssp@77600 POST_KERNEL 32 < /soc/dma@7c000 POST_KERNEL 40
...
Bumping up the SSP priority so the initialization is in sync with the
devicetree node hirearchy.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The set_brightness function of the led_pwm driver uses a default PWM
period (defined in the pwms DT property) to compute a pulse passed to
the pwm_set_pulse_dt function. If this default period is greater than
2^32/100 nanoseconds (about 43 milliseconds) then the calculation may
overflow.
This patch prevents this overflow by running the pulse computation under
a cast with a larger type (uint64_t).
Reported-by: Scott Worley <scott.worley@microchip.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Add a Kconfig to have the ability to fine tune the amount of RAM that
the driver uses based on the number of channels expected to be used.
Most of the code is already there but just need this Kconfig to get the
benefit of it by reducing the size of the statically created arrays.
Also change the number of channels field in the configuration to a byte
instead of a 32 bit integer because that should be sufficient to
describe the number of DMA channels.
Rename LPC DMA Driver Kconfigs with namespace to MCUX_LPC
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Setting higher priority to reset controller to initialize it before
other dependent drivers running at CONFIG_KERNEL_INIT_PRIORITY_DEFAULT
priority which is 40.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
The rv32m1 pinctrl driver depends on clock controller, add a new symbol
and set it so it gets initialized after that, and before other devices.
Fixes:
$ west build -p -b rv32m1_vega_ri5cy tests/kernel/common \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /soc/pinmux@41037000 PRE_KERNEL_1 1 < \
/soc/clock-controller@41027000 PRE_KERNEL_1 30
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The Kconfig IEEE802154_NRF5_MULTIPLE_CCA option is added.
The new functions `z_ieee802154_nrf5_extra_cca_attempts_set` and
`z_ieee802154_nrf5_extra_cca_attempts_get` are added.
The ieee802154_nrf5.c is updated allowing to pass extra cca attempts
to nRF 802.15.4 Radio Driver.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
The macro used in an assert statement in the `sys_mm_drv_page_phys_get()`
function was using an older version of the naming scheme, fixed now.
Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
TI K3 family of SoCs requires an extended set of registers to operate.
Extended functionality of the current driver to support the variant.
Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
Convert the GT911 driver to the input subsystem, fix the existing boards
to work in the default config.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Flash API states that drivers should support write requests without
any restrictions on location or alignment of the source buffer.
Due to hardware limitations of the QSPI peripheral, the nrf_qspi_nor
driver currently fails to perform a write from a RAM buffer that is
not word-aligned. Fix this by using in such case the same mechanism
that is used when the source buffer is located in the internal flash
(copy data to a buffer located on stack).
Also correct the length parameter for writes from this stack-based
buffer to be the actual data chunk length, not always the size of
the buffer (as for CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 4
this may lead to overwriting of some data located next in the flash).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add UDC driver for STM32 based MCU, relying on HAL/PCD.
This has been tested with cdc_acm sample on the following boards:
- 96b_carbon (STM32F4)
- disco_l475_iot1 (STM32L4)
- nucleo_wb55rg (STM32WB)
- nucleo_h723zg (STM32H7)
- stm32f3_disco (STM32F3)
This fails at runtime for the following:
- b_u585i_iot2a (STM32U5)
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Add a semaphore to ensure that only one transaction
happens at a time when threads want to transfer
simultaneously.
Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
Cache the delimiter string length in `parse_params`, instead of
calculating it on each character in the match buffer.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Given the following response: `+CIPSTA:ip6ll:"FE80::EDC:7EFF:FEDD:110C"`
The response delimiter is `:`, but there is also a quoted string that
contains the delimiter character. These delimiters should not be
considered when searching for the end of a parameter.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This adds support for the bosch bmi085 and bmi088. This also includes
support for data sync mode.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
When the image is chain-loaded, clocks may already by initialized.
The driver was lacking support for already configured HSE and
PLL sources. When CONFIG_ASSERT=y get_startup_frequency was
failing since it did not recognize these sources.
It's the same issue that was addressed in #58109 for stm32u5.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
Check and propagate two return values.
Don't need to check return of the part id request, but make
sure that the value is initialized before the comparison.
Fixes#58575
Coverity-CID: 316152
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The return value is consciously not checked, because the operation
is expected to fail. And the real request is executed afterwards.
Fixes#58593
Coverity-CID: 316443
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This patch adds support for PWM blink which is found in intel's
PCH hardwares.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Changes the Kconfig option to allow disabling mutex support, this
is to allow other Kconfig options to disable the feature.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Change the default mbox initialization priority so that it initializes
before ipc, as some ipc drivers depends on it.
Found with:
$ west build -p -b nrf5340dk_nrf5340_cpuapp \
samples/subsys/ipc/ipc_service/icmsg_me \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /ipc/ipc1 POST_KERNEL 46 <
/soc/peripheral@50000000/mbox@2a000 POST_KERNEL 50
ERROR: /ipc/ipc0 POST_KERNEL 46 <
/soc/peripheral@50000000/mbox@2a000 POST_KERNEL 50
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The underlying HAL driver may improperly forward an samplerdy event even
if it's disabled in the configuration. Ignore the event to prevent error
logs until the issue is fixed in HAL.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
remove the sdk based TOTAL_DMA_CHANNELS macro and instead just use the
zephyr driver's num_of_channels field
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
When reading multiple ADC channel in parallel, an ADC command chain will be
build. This is similar to a linked list, as every command references the
next command.
Before this patch every ADC command after the first, would always reference
this initial command. So that during execution only two commands (the last
and first) would be executed which resulted in readout of only two analog
values. As Zephyr expected more to come in, the `read_adc` function would
block endlessly.
The patch fixes the behaviour and allows a correct chain to build up.
Signed-off-by: Elisabeth Friedrich <auxsys@flowerpot.me>
PCIe devices refer to interrupt nodes, but are initialized with the same
priority, making the sequence depending on the linking order. Add a new
symbol and set it to one unit after intc to ensure that the
initialization sequence is stable.
Found with:
west build -p -b qemu_cortex_a53 \
samples/drivers/virtualization/ivshmem/doorbell \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /soc/pcie@4010000000 PRE_KERNEL_1 40 <
/soc/interrupt-controller@8000000/its@8080000 POST_KERNEL 40
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The intc_gicv3_its driver is currently initializing in POST_KERNEL, but
PCIe device nodes depends on it and are initialized earlier. Change the
init level to PRE_KERNEL_1 to sort that out, and also put the driver in
line with other interrupt controller drivers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The eSPI, I2C, and SPI emulators use devicetree macros to build an array
of devices on the virtual bus. Currently, they will add device nodes that
are not status-okay. This leads to linker errors because the respective
device drivers would not have instantiated device structs for these
nodes --assuming the driver was even compiled. This can be frustrating
if nodes need to be disabled for debugging or configuration purposes.
Update the bus emulators to only consider status-okay nodes by changing
the macros used to iterate over bus devices.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
Removed the unneccessary casts in the functions to remove warnings
during build for SoCs using RAT. Functionality reamins the same,
tested on board.
Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
With NEORV32 v1.8.2 the UART module was changed to a simpler
implementation. This updates the UART driver for the open-source NEORV32
RISC-V compatible processor system (SOC).
Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
