Add a Kconfig option for enabling the DAC test output. On the NXP
KE1xF the DAC test output is internally routed to ADCx SE23.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add support for STM32L0X using the generic STM32 backend. This is
quite a significant change since the L0 series uses a slightly
different flash controller. Refactor the generic backend to better
support different block sizes and the L0's register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Several STM32 chips have identical chip-specific code that has been
duplicated in different source files. Unify the F0x, F1x, and F3x to
use a single implementation.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
ringbuf claim API returns pointer to contiguous area. In cases when data
in ringbuf wraps the end of internal buffer, then single call to claim
data is not enough to get all data - there is remaining part on the
beginning of internal buffer. Those remaining bytes will need to wait
for next ISR handler to trigger workqueue. Theoretically this means that
data on the beginning of ringbuf can wait there forever, or simply to
the next timeout in PPP stack when data traffic continues.
Consume data from ringbuf in a loop, stopping only when claiming results
in empty buffer. This will make sure that there is no stale data in the
ringbuf.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Claimed ringbuf bytes were parsed until first frame was detected, but
remaining data in the claimed area was just ignored / lost.
Continue parsing bytes to the end of claimed area after each detected
frame.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
CLOCK_STM32_PLL_XTPRE Kconfig symbols was made to differentiate
code between F1 soc variants with XTRE and others.
It appears that specific XTRE code handling is already in place in
LL_PLL_ConfigSystemClock_* functions that are called afterwards.
Since this piece of code is not required anymore, let's remove
the symbol.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
- Fix passive mode protocol selection depending on AT versions
- Use Kconfig value for reset timeout
- Fix bug with parsing security from scan result
- Re-order some AT commands during init due to some commands having
dependency on other commands
Signed-off-by: Tobias Svehagen <tobias.svehagen@gmail.com>
Implemented rf2xx_set_txpower() in ieee802154_rf2xx.c by mapping dBm
values to RF2XX register values.
Signed-off-by: Kari Severinkangas <kari.severinkangas@tridonic.com>
Signed-off-by: Markus Becker <markus.becker@tridonic.com>
Remove K_FOREVER wait on completion_sync.
In some situations (a short on I2C SDA line for example), this
semaphore will never be released and therefore we should not wait
it forever.
Instead we wait for a maximum of 100msec and return an error if we
weren't able to retrieve the semaphore.
In such situation, the program is not stuck anymore, but the I2C
driver must be uninit then init again to work again.
Fixes#25076.
Signed-off-by: Xavier Chapron <xavier.chapron@stimio.fr>
The driver should only call net_pkt_unref on packets that get
successfully handled, ie where send/sendto return 0. If the packet
cannot be handled, net_context layer still owns the packet and should
take care or the unref.
Signed-off-by: Tobias Svehagen <tobias.svehagen@gmail.com>
The Atmel GMAC Ethernet driver may be used by both the SAM series
(e.g. SAM E70) and SAM0 series (e.g. SAM E54) SoCs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
When writing buffers larger then page-size, there is already a routine
that checks wrap around and adjusts offsets, but this routine was
missing incrementing the data pointer, which would results in
rewriting the same page-size bytes over and over. This adds the proper
increment code.
Signed-off-by: Fabio Utzig <fabio.utzig@nordicsemi.no>
Silence a gcc warning due to possible return of unitialized variable in
erase function. This could only happen if size == 0, which doesn't seem
likely, but initializing the variable to zero should fix the issue.
Signed-off-by: Fabio Utzig <fabio.utzig@nordicsemi.no>
Add support for the SX126x series of LoRa radios using the
LoRaMAC-Node HAL.
This driver currently makes the following assumptions:
* DIO1 is used as an interrupt line.
* There is an RF switch selecting between the TX and RX ports and
that switch is controlled by DIO2.
* There is either no TCXO or the TCXO is controlled by DIO3.
Specifically, the limitations above mean that modules that use GPIOs
to control the RF switch are currently not supported. Support for such
modules would need changes to the LoRaMAC-Node code.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Add a new configuration option, LORA_SX12XX, that is shared for all of
the LoRaMAC-node-based radio drivers. By default, the appropriate
driver for the LoRa radio in the device tree is included is included
in the build.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Some boards may include an APA102 LED on an existing SPI bus. With
additional circuitry, chip select is supported where the APA102
lacks a built in CS pin.
This patch allows CS to be defined in the devicetree (through .dts
files) and utilised in the apa102.c driver if it's available. Preserving
old behaviour if no chip select is defined.
Signed-off-by: Roman Vaughan <nzsmartie@gmail.com>
Adds optional device tree properties to set delays between spi chip
select assert/deassert and clock edges in the mcux dspi and lpspi
drivers. If these properties are not set, then the minimum supported
delays are used.
Verified that tests/drivers/spi/spi_loopback/ still passes on
mimxrt1050_evk (lpspi driver) and frdm_k64f (dspi driver).
Measured with a scope that the pcs-sck-delay and sck-pcs-delay times on
the first spi transaction in the test are reduced from 7.82 us to 20 ns
on mimxrt1050_evk.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add an additional option to the spi_cs_control struct that records how
the pin has been configured in devicetree. For drivers that are not
updated, the CS behaviour is the same as before (Push-Pull).
Use the devicetree knowledge with the GPIO subsystem so that the correct
physical pin levels for the CS pin are automatically selected.
Fixes#26267
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
PCIe shell was enabled by default if shell is enabled in below commit:
commit ee985d81aa ("shell: enable modules by default if shell is
enabled").
However, this shell file has tests for PCIe RC, not applicable to EP.
So, should not be default enabled for PCIe EP.
If we add EP shell tests in future, they should be added under
drivers/pcie/endpoint/ directory.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This runs the Timer/Counter for Control in 'normal' PWM mode. The
number of channels and counter width depends on the device and is
imported from DeviceTree.
Signed-off-by: Michael Hope <mlhx@google.com>
