Modifications to incorporate latest write to new flash area
Modification to avoid writing garbage to new flash area when compactor
is called during init.
Modifications to allow erase at partition size instead of eeprom
pagesize.
Modifications to better separate rambuf usage from flash usage.
Corrected some errors in compactor
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
This driver emulates a EEPROM device in flash.
Reworked implementation with modified flash layout.
The emulation represents the EEPROM in flash as a region that is a
direct map of the eeprom data followed by a region where changes to
the eeprom data is stored. Changes are written as address-data
combinations. The size of such a combination is determined by the
flash write block size and the size of the eeprom (required address
space), with a minimum of 4 byte.
The eeprom page needs to be a multiple of the flash page. Multiple
eeprom pages is also so supported and increases the number of writes
that can be performed.
The eeprom size, pagesize and the flash partition used for the eeprom
are defined in the dts. The flash partition should allow at least two
eeprom pages. For fast read access a rambuffer can be enabled for the
eeprom (by setting the option rambuf in the dts).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
CAN_SYNC_SEG and ts1 are in common units. Both need to be scaled by 1000
to calculate the sample point.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In the npcx i2c FIFO mechanism, the hardware will release SCL bus
immediately after the driver reads data from FIFO. That's why we need
to hold SCL bus before configuring the next transaction. Once it was
done, the driver release the bus for the next transaction.
But during the last transaction, the driver releases SCL first then
starts a STOP condition. At this moment, the SCL is pulled high by PU
resistance and driven to low for generating STOP condition later. This
additional clock might influence some i2c devices if they don't reset
their state machine after receiving STOP.
This CL fixes this issue by two steps:
1. Distinguish that it's the last read transaction with STOP condition?
2. If so, issue STOP condition before reading FIFO instead of holding
SCL bus. Then the hardware will generate it immediately after reading
FIFO.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The definition to check if timers have up to 6 channels was causing
warnings when -Wexpansion-to-defined was enabled.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The first uart instance was already devicetree based. To be consistent
convert the second instance to also be devicetree based.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
QDEC_NRFX shall depend on either HAS_HW_NRF_QDEC,
or HAS_HW_NRF_QDEC0, since in the nRF5340 Application
core definition we select HAS_HW_NRF_QDEC0 instead of
HAS_HW_NRF_QDEC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
While running certain peci command, observed when FW attempts
to read last byte (Response FCS), PECI host controller returned
“Read FIFO” empty. Since “Read FIFO” is empty FW didn’t read
the response FCS.
Due to this issue, FW getting corrupted response from the PECI
controller for all the subsequent PECI commands.
To address this issue, FW waits for “Read FIFO” filled up by
the PECI controller.
Signed-off-by: Diwakar C <diwakar.c@intel.com>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This fixes a missing bit in the registers description
which results to wrong FIFO ODR configuration
when trying to configure a FIFO ODR higher than 833Hz
Signed-off-by: Clotilde Sattler <clotilde.sattler@stimio.fr>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a follow-up to commit 9f56cc5531.
Add net/ in the inclusion of ieee802154_radio.h so that the file can
be successfully included.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The CMSDK uart interrupts for TX and RX can either be treated as a
signel interrupt line or distinct interrupts for TX & RX. In the case
that they were distinct we didn't get the ifdef correct based on DTS.
If we have 2 interrupts in DTS we assume they are for TX & RX and thus
build the interrupt support for distinct TX & RX ISRs.
Also, cleanup handling of UART_2..UART_4 to be similar to how
UART_0/UART_1 code is using DT_INST_IRQN(x).
Fixes#30770Fixes#25601
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
A recent patch removed use of the cfg structure, but left a pointer to
it defined which causes build failures.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The NPCX clock driver was already using devicetree, just need to make a
small tweak to use DEVICE_DT_INST_DEFINE and update NPCX_CLK_CTRL_NAME
to match the label for the "nuvoton,npcx-pcc" clock controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a simple pinctrl node for the IOF registers under the GPIO
controller node to be used by the pinmux driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert esp driver:
NET_DEVICE_OFFLOAD_INIT -> NET_DEVICE_DT_INST_OFFLOAD_DEFINE
DT label is already required, so use it and drop CONFIG_WIFI_ESP_NAME
option.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Convert ublox-sara-r4 driver:
NET_DEVICE_OFFLOAD_INIT -> NET_DEVICE_DT_INST_OFFLOAD_DEFINE
DT label is already required, so use it and drop
CONFIG_MODEM_UBLOX_SARA_R4_NAME option.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This include make possible to use the arm_arch_timer on
platform such as Cortex-A9 or Cortex-R7 which has support for
ARM Global Timer.
The global timer is a 64 bit incrementing counter, memory-mapped
in the private memory region.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
In some cases we cannot know the BDF up-front, so provide a way to
look it up based on the vendor and device ID.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
These have been redefined in various places - better to have them in a
single place that different users can use.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add ESPI SAF features to the Microchip eSPI driver as
a separate file. ESPI SAF depends upon the core eSPI
driver adding the ability to attach the system SPI
flash to the EC eSPI endpoint instead of the host
eSPI controller.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
During the driver init, the function will set the sensor resolution
based on the driver's dts variable "resolution"
The driver's device tree has been updated to include the value
"resolution".
The default is set to the highest resolution of 0.0625C.
Moved mcp9808_reg_write from mcp9808_trigger.c to mcp9808.c
This allows resue of the same function in both the trigger and
resolution functions.
Function name changed to xxx_16bit to distinquish it from the 8
bit write function that will added.
Signed-off-by: Steven Daglish <s.c.daglish@gmail.com>
In this CL, npcx_miwu_interrupt_configure is no longer responsible for
turning the interrupt off. Although the default state of WK_EN is
disabled, the users still have the chance to configure them when WK_EN
is enabled via npcx_miwu_irq_enable(). Hence, this CL also ensures that
WK_EN is disabled before configuring them.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL uses a simpler configuration approach that turns GPIO's
interrupts off instead of calling npcx_miwu_interrupt_configure
with NPCX_MIWU_MODE_DISABLED.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
