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24538 commits

Author SHA1 Message Date
Jay Vasanth
3034693509 drivers: i2c: MEC15xx: Improved error handling
1. Check I2C Clock and Data is high through GPIO driver instead
of the I2C bitbang registers
2. i2c_xec_poll_write() and i2c_xec_poll_read() will poll to
check I2C clock and data lines are high before initiating the
transaction. The polling will be every 25us for a cumulative
max of 2.5ms
3. wait_completion() will not call recover_from_error() to reset
the controller. Instead will poll for 10ms for the PIN bit to
clear before returning error.
4. wait_completion() will send STOP if the 9th bit is NACK
5. If any errors with current transaction:
(a) Set error_seen flag.
(b) In the next transaction do the recovery process (reset the
i2c controller) if the clk and data lines are high.
Note: error_seen flag is set for Address NACK with Repeated
Start as well.
6. If timeout error occurs in wait_completion():
(a) Set timeout_seen flag;
(b) Wait till the slave will release the clock.
(c) Once slave releases clock send STOP on the bus. If the
timeout occurred while master read, read the I2C DATA register
for the hardware to proceed.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 14:13:34 -05:00
Bartosz Bilas
718225dadf drivers: ethernet: dsa_ksz8xxx: fix spi bus initialization
spi_dt_spec structure initialization should not be done
in the runtime during spi bus initialization because it
causes kernel panic.

Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
2022-03-07 09:54:21 -06:00
Rafał Kuźnia
1a0fed70d5 drivers: timer: Set user RTC channel count conditionally
The RTC user channel count is increased contitionally to 2 when
nrf_802154 radio driver is enabled.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2022-03-07 09:26:52 -06:00
Rene Bredlau
876ea8d215 modem: hl7800: use correct timeouts on KTCPSND to avoid internal deadlock
The response of a KTCPSND has two phases. According to documentation by
wireless the timeout is 60 seconds. The fix respects the timeout on the
second phase, too (waiting for OK or errors from modem). Previously only
the first phase used 60 seconds and the second phase used 5 seconds.

Without this fix the hl7800 will lock the tcp stack for the current
socket indefinitely if another socket operation is performed before the
response from the modem is received.

Additionally all timeouts are adjusted to be at least one second longer
as the documented timeout from wireless. This avoids races between the
hl7800 and the driver.

Signed-off-by: Rene Bredlau <git@unrelated.de>
2022-03-07 09:24:25 -06:00
Andrzej Głąbek
70a9e2055c drivers: Remove undesirable irq_enable calls from nrfx driver shims
Shims for nrfx drivers should only connect the related IRQ handlers,
they should not enable the IRQs, as this could lead to a situation
where the interrupt handler is called before the driver had a chance
to properly initialize the peripheral and install the provided event
handler. nrfx drivers will enable the interrupts appropriately on
their own by calling the NRFX_IRQ_ENABLE macro which is implemented
in nrfx_glue.h as a call to irq_enable().
This commit fixes the above issue spotted in the following shims:
- dmic_nrfx_pdm
- clock_control_nrf
- i2s_nrfx

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-03-07 09:19:56 -06:00
Erwan Gouriou
d74cb2a3df drivers/clock_control: stm32h7: Simplify SysClk freq computing
Instead of reading registers query the info on sysclock configuration
from existing configuration symbols.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-07 11:36:28 +01:00
Erwan Gouriou
2116606ce2 drivers/clock_control/stm32h7: Independent clocks configuration
Rework clock start up functions in order to allow configuration
and enabling of individual clocks.
This way, each clock defined with a "okay" status will be enabled
even if not part of the sysclock clock tree.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-07 11:36:28 +01:00
Erwan Gouriou
ceb8579854 include/drivers/clock_control: stm32: Add XXX_ENABLED and XXX_FREQ
Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks:
HSI, HSE, MSI(S), CSI, LSI, LSE..

Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible
replace by new STM32_LSE_ENABLED when making sense.

Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED

Additionally, add STM32_PLL_FOO_ENABLED definitions.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-07 11:36:28 +01:00
Erwan Gouriou
348070e4ea drivers/clock_control: stm32u5: Use LL API for LSESYS programming
Use LL API when possible.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-07 11:36:28 +01:00
Erwan Gouriou
5a1fe914ff drivers/clock_control stm32h7: Move RCC HW semaphore unlock
PLL3 setting should also be protected CFG_HW_RCC_SEMID.
Move semaphore unlock after we're done with PLL3.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-07 11:36:28 +01:00
Erwan Gouriou
87eba815dd drivers/clock_control: stm32h7: Complementary readability changes
- Factorize elementary clocks setup code.
- Put conditional logic on CONFIG_CPU_CORTEX_M4 outside init function

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-07 11:36:28 +01:00
Erwan Gouriou
12404f7668 drivers/clock_control: stm32h7: Make driver more readable
Re-arrange code using benefits of IS_ENABLED.
Change some #if to #ifdef when possible.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-07 11:36:28 +01:00
Erwan Gouriou
a911b81a2e drivers/clock_control: stm32u5: Make driver more readable
Use benefits of IS_ENABLED.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-07 11:36:28 +01:00
Jay Vasanth
73f24056d5 kscan: update mchp keyscan module to use pinctrl
Changes to keyscan module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
9138d81365 adc: updates to MEC172x adc to support pinctrl
Changes to adc module to support pinctrl.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
535c20e490 qmspi: MEC172x: fix unused variable warning
Fix unused variable warning when CONFIG_SPI_ASYNC
is not defined

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
99c89ebb78 qmspi: update MEC172x qmspi module for pinctrl
Changes to qmspi module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
156440f3f0 serial: update mchp uart module to use pinctrl
Changes to uart module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
f8130d5ce3 espi: updated MEC172x espi module for pinctrl
Changes to espi module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
63ac835988 i2c: update MEC172x i2c module for pinctrl
Changes to i2c module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
5cccbb13bc gpio: MEC172x: update gpio module for pinctrl
Changes to gpio module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
2cd02bd826 drivers: pinctrl: Microchip MEC172x pinctrl driver
Add core files for Microchip MEC172x pinctrl driver

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Sylvio Alves
a4a2b9f1cd pinmux: esp32: check only for pullup
Current implementation checks for pulldown and
pullup. As pinmux configuration is related to PU only,
this PR checks for PU feature instead of PD.
This also fix missing PU check when PD is present.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-03-07 10:54:18 +01:00
Dino Li
d8c2c2cbb8 it8xxx2: timer: to unified method of enabling event timer.
This enable timer and also reset it.

fixes #42851
fixes #42953

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-03-07 10:51:29 +01:00
Artur Hadasz
5451c8b70f modules: hal_nordic: 802.15.4 make possible to disable CSMA-CA
Currently if an attempt to disable CSMA-CA in by setting an
appropriate flag in another (for example application)
CmakeLists.txt it caused lots of warnings. This fix allows
higher level CMakeLists.txt to disable CSMA-CA without
warnings.

Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
2022-03-07 10:51:21 +01:00
Francois Ramu
8e99151937 drivers: entropy: stm32 rng driver should not block if Seed error occurs
When a Seed error occurs during the random nb generation,
the driver tries to recover and exit without providing a random data
This avoids looping endlessly on the DRDY bit of the RNG status reg
because it remains 0 in case of error.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-03-07 10:49:19 +01:00
Andrew Hedin
c64783f29d drivers: sensors: lis2dh: Allow any movement on interrupt 1
Allow movement detection to be used on hardware
that only has one interrupt line connected.
Change hardware configuration to a bitmask.

Signed-off-by: Andrew Hedin <andrew.hedin@lairdconnect.com>
2022-03-07 10:46:17 +01:00
Gerard Marull-Paretas
ee30559f07 soc: arm: nuvoton_npcx: s/SOC_POWER_MANAGEMENT_TRACE/NPCX_PM_TRACE
Rename CONFIG_SOC_POWER_MANAGEMENT_TRACE to CONFIG_NPCX_PM_TRACE so that
it is clear that it's a NPCX specific option.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-04 09:05:45 -06:00
Tim Lin
056738514a ITE: drivers/adc: implement ADC channels 13-16
The ADC driver of IT81302 chip can support channels 0-7 & 13-16.
This PR adds to implement ADC channels 13-16.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-03-04 09:03:04 -06:00
Gerard Marull-Paretas
cb9a279050 drivers: dma: dw_common: fix style issue
Fix a couple of issues reported by checkpatch:

ERROR:POINTER_LOCATION: "(foo*)" should be "(foo *)"

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-04 08:55:45 -06:00
Emil Lindqvist
8b4a3e2328 sensor: vcnl4040: add missing semicolon
Adding missing semicolon to vncl4040 driver

Signed-off-by: Emil Lindqvist <emil@lindq.gr>
2022-03-03 18:52:28 -05:00
Daniel DeGrasse
1fd4205eee drivers: serial: Add pinctrl support to mcux uart driver
Add pinctrl support to mcux uart driver

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-03 13:00:20 -06:00
Daniel DeGrasse
fc8877187e drivers: pinctrl: Add kinetis pinctrl driver
Add kinetis pinctrl driver. Driver initializes clocks for each port, and
exposes the pinctrl_configure_pins function required for pinctrl
support.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-03 13:00:20 -06:00
Kamil Piszczek
cf6a58d3f6 bluetooth: hci: rpmsg: use ipc service library
The Bluetooth HCI driver based on the RPMsg transport now uses the IPC
service module. The compatible Bluetooth sample - HCI RPMsg - has also
been migrated to the new IPC solution.

Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
2022-03-02 17:03:01 +01:00
Carlo Caione
5e810dd34d mbox: Fix function syscall check
The syscall check is done using a wrong function name. Fix it.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-03-02 07:55:32 -08:00
Dino Li
7a9a5cec0b it8xxx2: espi: reduce h2ram pool size
This saves 1280 bytes memory space by default eSPI configurations.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-03-02 09:45:14 -06:00
Krzysztof Chruscinski
d13ab8b367 drivers: mbox: Add configurable init priority
Add configurable initialization priority.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-03-02 09:42:09 -06:00
Flavio Ceolin
d2a56c5047 drivers: crypto: Add multipart hash support
Add a new API to support multipart hash calculation. The API allows
split the data input to be split in small chunks.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-03-01 16:32:43 -05:00
Flavio Ceolin
64f6a5ec37 drivers: crypto: mtls: Add support for hashing
Add support for hashing on mtls driver.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-03-01 16:32:43 -05:00
Flavio Ceolin
981ea3042e drivers: crypto: Keep namespace consistent
The API to set a callback has the namespace cipher but the driver
function pointer was using the namespace crypto. As this API belongs
to the cipher subgroup, just rename the function pointer in the driver
to be consistent.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-03-01 16:32:43 -05:00
Flavio Ceolin
ce48b8c3d1 drivers: crypto: s/cipher_struct/cipher
Just give a better name to this file since now we have changed the
file where crypto driver API is defined.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-03-01 16:32:43 -05:00
Flavio Ceolin
df3d1f83f7 drivers: crypto: Rename cipher file
This file defines the crypto driver API, cipher is supposed to be just
one type of capability (other can be hash) of these drivers, just
change the file name to be consistent with it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-03-01 16:32:43 -05:00
Flavio Ceolin
d1628ba035 drivers: crypto: Add cipher namespace in some API
Add 'cipher' namespace in some in the driver API since these
operations are for cipher.

Set a namespace to make it clear that these are cipher operations,
this allow further functionalities, like hash, to be added in this
driver API.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-03-01 16:32:43 -05:00
Casper Meijn
2eb1feea91 drivers: display: st7789v: fix gpio_dt_spec initialization
The `gpio_dt_spec` structures where never initialised, therefore the driver
would always fault with "E: Reset GPIO device not ready" printed to the
console.

Fixes: 069bf6be44
("drivers: display: st7789v: use gpio_dt_spec")

Signed-off-by: Casper Meijn <casper@meijn.net>
2022-03-01 14:38:21 -06:00
Qingsong Gou
b0eb3207a9 drivers: kscan: add support for cst816s touch panel driver
Add touch panel driver support for pinetime

Signed-off-by: Qingsong Gou <gouqs@hotmail.com>
2022-03-01 14:24:27 -06:00
Aymeric Aillet
732f829f69 drivers: pinctrl: rcar: Rework pin configuration
Rework pin configuration to meet documented procedures.
3 procedures are covered here:
  - GPIO -> Peripheral (+select peripheral function)
  - Peripheral -> GPIO
  - Change from Peripheral function 1 -> Peripheral function 2

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-03-01 12:20:25 -08:00
Jay Vasanth
8c193743ac drivers: bbram: mec: fixed compilation error
Fixed compilation error when building bbram driver
for MEC15xx

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-01 14:18:55 -06:00
YuLong Yao
344e7284c3 drivers: pinctrl_gd32_afio: add header file.
add soc.h include in pinctrl_gd32_afio.c

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2022-03-01 18:06:14 +01:00
Andy Ross
27a59ec9d5 drivers/ipm: Add ipm_cavs_host: host/DSP communication on adsp_intel
Intel Audio DSPs have "IPC" interrupt delivery and shared memory
window hardware.  The Sound Open Firmware project has historically
used the combination of these to implement a bidirectional
message-passing interface.  As it happens, this protocol is an
excellent fit for Zephyr's somewhat geriatric but still useful IPM
interface.

This implements a SOF-protocol-compatible transport that will
hopefully prove a bit more futureproof for non-Intel SOF
architectures.  It is a software-only device, built on top of the
underlying SOC APIs for the SRAM windows (in cavs-shim) and IPC
(cavs_ipc).

Note that SOF actually has two protocol variants (ipc3 and ipc4): in
both, the command header (passed as the "id" parameter in IPM) is sent
via the hardware doorbell register.  But in ipc4, the second hardware
scratch register is used to transmit the first four bytes of the
command before involving the SRAM window (in ipc3, it's ignored).
Both modes are supported by this driver, set IPM_CAVS_HOST_REGWORD to
choose the "ipc4" variant.

Finally: note that the memory layout for the windows in question is
inherited from SOF, and for compatibility (with both SOF and with the
offsets used by the host!) these can't be changed without major
surgery.  They're defined in kconfig, but should be treated as
read-only until we get a chance to rework the way Zephyr does its SRAM
window management (and probably in concert with the host drivers).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-03-01 09:59:15 -05:00
Andy Ross
ebf48d7112 drivers/ipm: Add IPM_CALLBACK_ASYNC mode
Some IPM devices support asynchronous command processing, where
acknowledgment of an IPM message can be delayed while handling
happens in a context other than the ISR that invoked the callback.
Expose this via a kconfig that can be selected by the driver, and add
a new "complete" call (a zero-overhead stub on non-supporting devices)
to signal the end of message handling.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-03-01 09:59:15 -05:00