This commit adds support to select pll outputs as peripheral clock
sources to the stm32 common driver.
With this commit they are only available on
STM32G0, STM32G4, STM32L4, STM32L5, STM32WB, and STM32WL.
Support for STM32F2, and STM32F4, which also have p,q,r dividers,
is not enabled in this commit.
Also, stm32_clock_control_get_subsys_rate is extended to return
the configured frequency in case they are enabled, otherwise 0.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit configures the PLL_P divider for SOCs compatible to the
stm32_ll_common driver in case a value was defined via a dts property.
Additionally, in case the divider value is defined in the device
tree, the respective pll output is enabled during initialization
in set_up_plls().
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In the stm32_ll_common driver the PLL_Q divider should not
be directly written to RCC->PLLCFGR->PLLQ, but should be
translated to the matching register value.
i.e. shifting the value to the correct position of the register
is not enough.
This commit makes sure the divider value taken from device tree, is
correctly translated ot the matching register register value by
converting it to a STM32CUBE LL definition LL_RCC_PLLQ_DIV_xx.
Typcial divider to register value mapping:
G0, WB, WL:
Dividers 2-8 mapped to register values 1-7(0 reserved).
G4, L4, L5:
Dividers 2,4,6,8 mapped to reg values 0,1,2,3.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
All these series share the same defines, and while they are not used
by all socs of the common-driver, this is not exptectd to lead to
any conflict.
By moving the defines they can also be used in clock_stm32_ll_common.c
Additionally, the stm32g0 pll_div define was renamed to pllm
in order to match the other series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The STM32_SRC_CLOCK_MIN and STM32_SRC_CLOCK_MAX defines
are not really needed because non valid clock sources are already
filtered out by the precompiler.
Only STM32_SRC_CLOCK_MIN was used once in code and can be replaced.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit fixes a bug where an already received Rx frame could not be
processed by the IEEE 802.15.4 driver.
In the current implementation, buffer is marked as free and released to
the buffer pool after `nrf_802154_buffer_free_raw` finishes executing.
However, delays caused by thread scheduling might result in a new frame
being already received and provided to the driver before
`nrf_802154_buffer_free_raw` returns. Such a situation ends in an
assertion now.
This commit changes that behavior by marking the buffer as free before
calling `nrf_802154_buffer_free_raw`.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
This commit increases verbosity of serialization error handler for
nRF5340 application core. The handler prints the error code now.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
As we work to phase out devicetree 'label properties, convert
driver to just use dev->name instead of DT_INST_LABEL.
Signed-off-by: Kumar Gala <galak@kernel.org>
Instead of using or'ed list of Kconfig options listing the compatible
series with what can be called "stm32h7 variant", use the matching
compatible information.
This will prevent to update the driver next time that a compatible series
is ported into zephyr.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
If the preprocessor constant ESP_MAX_DNS is defined as 0,
Coverity reports a condition that can never be true, and some
dead code as well. This also violates MISRA rules on dead code.
This is caused by this segment in drivers/wifi/esp_at/esp.h:
#if defined(CONFIG_WIFI_ESP_AT_DNS_USE)
#define ESP_MAX_DNS MIN(3, CONFIG_DNS_RESOLVER_MAX_SERVERS)
#else
#define ESP_MAX_DNS 0
#endif
Fix this by never setting ESP_MAX_DNS to 0, as is the currently
case. Define ESP_MAX_DNS only if it is configured through
CONFIG_WIFI_ESP_AT_DNS_USE and CONFIG_DNS_RESOLVER_MAX_SERVERS:
#if defined(CONFIG_WIFI_ESP_AT_DNS_USE)
#define ESP_MAX_DNS MIN(3, CONFIG_DNS_RESOLVER_MAX_SERVERS)
#endif
Since CONFIG_DNS_RESOLVER_MAX_SERVERS is 1 or greater, ESP_MAX_DNS
will always be greater than 0.
If, on the other hand, ESP_MAX_DNS is not defined, relevant
functions will be reduced to empty stubs, since in that case
they do not make sense.
There could be a cleaner solution to this, but this one is the
least intrusive (involves less code changes).
Coverity-CID: 219490
Coverity-CID: 219513
Coverity-CID: 219520
Coverity-CID: 219524
Signed-off-by: Aleksandar Markovic <aleksandar.markovic.sa@gmail.com>
Some EFR32 SoCs use a secure element subsystem to manage
security features (i.e., TRNG, secure bootloader or cryptographic
functions).
This driver relies on the SE Manager high-level API provided by Silicon
Labs. The API interacts with the SE subsystem, provides helper functions
to achieve cryptographic operations and ensures that only one operation
is running at a time by using mutexes and semaphores.
Instead of relying on the SE Manager from Silicon Labs, one could
recreate the behaviour of the Manager and put the code in the crypto
driver folder and create a dependency for other drivers using the crypto
manager (e.g., keys, entropy).
I went for the SE Manager API as it is already there and supported by
Silicon Labs.
Tested using the random subsystem.
Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
The clock of the octospi peripheral is directly defined
by the DTS and configured by the clock_control_on function.
No specific stm32cube function is required then.
The clock control is taking this clock source to calculate
the clock rate.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Move from using Kconfig NET_PPP_UART_NAME to a devicetree chosen
property ("zephyr,ppp-uart"). This is similar to a number of other
functions like "zephyr,shell-uart" or "zephyr,bt-uart".
As part of this we rework the init code a little to use
DEVICE_DT_GET for the modem gsm-ppp case.
Signed-off-by: Kumar Gala <galak@kernel.org>
Rather than using a devicetree node label, utilize the driver
compat and thus DT_INST which is standard means for most drivers.
Signed-off-by: Kumar Gala <galak@kernel.org>
There is a build warning of unused `adc_stm32_oversampling_ratioshift`
function: [-Werror=unused-function]. This makes twister fail, as all
warnings are treated as errors.
Fix that by ifndef'ing adc_stm32_oversampling_ratioshift().
Fixes: c57a41c5d2 ("drivers/adc: stm32: do not disable the ADC if
resolution is unchanged")
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
As we work to phase out devicetree 'label' properties, convert
driver to just use sx126x instead of DT_INST_LABEL for logging
purposes.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move the `REQUIRES_FULL_LIBC` dependency from `config LORA` to
`config LORAWAN`. The commit that added the `select` (f590d4fa) mentions
that this is required by `loramac-node`, which is only used by LoRaWAN,
not the base LoRa code.
This results in small FLASH savings when compiling the samples, but can
result in larger savings in more complex applications:
```
// With REQUIRES_FULL_LIBC
west build -b 96b_wistrio zephyr/samples/drivers/lora/send/
[162/162] Linking C executable zephyr/zephyr.elf
Memory region Used Size Region Size %age Used
FLASH: 37708 B 128 KB 28.77%
SRAM: 8832 B 32 KB 26.95%
IDT_LIST: 0 GB 2 KB 0.00%
// Without REQUIRES_FULL_LIBC
[181/181] Linking C executable zephyr/zephyr.elf
Memory region Used Size Region Size %age Used
FLASH: 37444 B 128 KB 28.57%
SRAM: 8832 B 32 KB 26.95%
IDT_LIST: 0 GB 2 KB 0.00%
```
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Change logic in `modem_cmd_handler_setup_cmds` and
`modem_cmd_handler_setup_cmds_nolock` to always sleep
after each sent AT command.
The issue was found using a logic analyzer while debugging 'NO CARRIER'
from a BG95 modem while being in data mode.
The reason 'NO CARRIER' occured was due to crosstalk to DTR which
terminated data mode.
The logic analyzer also revealed that without the delay the next AT
command is sent before the whole 'OK\r\n' is received. This is not
addressed in this commit.
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/47082
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
In prepration for configuring I2C/SPI defaults at the board level,
change the DesignWare GPIO driver's clock gate option to depend on clock
control instead of selecting clock control. This breaks a Kconfig
dependency loop when adding the following to a board's
Kconfig.defconfig:
config SPI
default y if SENSOR
There aren't any in-tree users that enable the clock gate option, so
there aren't any places in-tree that now need to enable the clock
control driver. Out-of-tree users that set CONFIG_GPIO_DW_CLOCK_GATE=y
will now also need to set CONFIG_CLOCK_CONTROL=y.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
In preparation for extending samples/sensor/magn_polling to support
additional magnetometer drivers, enable these drivers by default when
the sensor driver class is enabled (CONFIG_SENSOR=y) and a compatible
devicetree node is enabled.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
The fxos8700 device supports 3 modes: accelerometer-only,
magnetometer-only, or hybrid (accelerometer and magnetometer) modes. The
accelerometer-only mode is register compatible with mma8451q, mma8652fc,
and mma8653fc, which allows the fxos8700 driver to be used with these
devices as well.
Most in-tree boards can use hybrid mode because they have the fxos8700
device, therefore we change the driver default to match the common case.
For the handful of boards that have an mma86xx or mma84xx device, we
override the driver default to accelerometer-only mode. As a result, we
can enable the magn_polling sample application for the fxos8700 driver
without having to add a bunch of board-specific configuration overlays
for hybrid mode.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
The I2C API recently updated terminology to replace "master" with
"controller", but this instance in the mcux lpi2c driver was missed.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
If hw-flow-control is set in the uart section of the device tree source,
it is read by gsm_ppp.c and AT+IFC=2,2 is sent to the modem.
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/46928.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Fix issue #45168.
When setting high bit timing, the controller is timing
out when trying to switch from an internal mode to another.
To fix this issue, we add some delay when switching modes.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
