drivers: Fix coding guidelines MISRAC:2012 Rule 14.4 do-whiles/Zero checks
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement and the controlling expression of an iteration-statement shall have essentially Boolean type.) Use `do { ... } while (false)' instead of `do { ... } while (0)'. Use comparisons with zero instead of implicitly testing integers. The commit is a subset of the original auditable-branch commit: 5d02614e34a86b549c7707d3d9f0984bc3a5f22a Signed-off-by: Simon Hein <SHein@baumer.com>
This commit is contained in:
parent
c1288208ce
commit
d0921018fc
32 changed files with 49 additions and 49 deletions
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@ -294,7 +294,7 @@ static const struct adc_driver_api cc32xx_driver_api = {
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adc_cc32xx_isr_ch##chan, \
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DEVICE_DT_INST_GET(index), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(index, chan, irq)); \
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} while (0)
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} while (false)
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#define cc32xx_ADC_INIT(index) \
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\
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@ -526,7 +526,7 @@ do { \
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adc->CALIB.reg = ADC_SAM0_BIASCOMP(n) \
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| ADC_SAM0_BIASR2R(n) \
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| ADC_SAM0_BIASREFBUF(n); \
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} while (0)
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} while (false)
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#else
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@ -551,7 +551,7 @@ do { \
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ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos; \
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adc->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | \
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ADC_CALIB_LINEARITY_CAL(lin); \
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} while (0)
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} while (false)
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#endif
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@ -846,7 +846,7 @@ static const struct can_driver_api mcux_flexcan_driver_api = {
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mcux_flexcan_isr, \
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DEVICE_DT_INST_GET(id), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(id, name, irq)); \
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} while (0)
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} while (false)
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#define FLEXCAN_IRQ(id, name) \
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COND_CODE_1(DT_INST_IRQ_HAS_NAME(id, name), \
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@ -398,7 +398,7 @@ static int dma_sam0_get_status(const struct device *dev, uint32_t channel,
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DT_INST_IRQ_BY_IDX(0, n, priority), \
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dma_sam0_isr, DEVICE_DT_INST_GET(0), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(0, n, irq)); \
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} while (0)
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} while (false)
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static int dma_sam0_init(const struct device *dev)
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{
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@ -718,7 +718,7 @@ DEVICE_DT_INST_DEFINE(index, \
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dma_stm32_shared_irq_handler, \
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DEVICE_DT_INST_GET(dma), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(dma, chan, irq)); \
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} while (0)
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} while (false)
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#else /* CONFIG_DMA_STM32_SHARED_IRQS */
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@ -737,7 +737,7 @@ static void dma_stm32_irq_##dma##_##chan(const struct device *dev) \
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dma_stm32_irq_##dma##_##chan, \
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DEVICE_DT_INST_GET(dma), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(dma, chan, irq)); \
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} while (0)
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} while (false)
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#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
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@ -98,7 +98,7 @@ static const char *e1000_reg_to_string(enum e1000_reg_t r)
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#define iow32(_dev, _reg, _val) do { \
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LOG_DBG("iow32 %s 0x%08x", e1000_reg_to_string(_reg), (_val)); \
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sys_write32(_val, (_dev)->address + (_reg)); \
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} while (0)
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} while (false)
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#define ior32(_dev, _reg) \
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({ \
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@ -1447,7 +1447,7 @@ static void eth_mcux_err_isr(const struct device *dev)
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DEVICE_DT_INST_GET(n), \
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0); \
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irq_enable(DT_INST_IRQ_BY_NAME(n, name, irq)); \
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} while (0)
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} while (false)
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#define ETH_MCUX_IRQ(n, name) \
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COND_CODE_1(DT_INST_IRQ_HAS_NAME(n, name), \
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@ -1465,7 +1465,7 @@ static void eth_mcux_err_isr(const struct device *dev)
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DEVICE_DT_INST_GET(n), \
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0); \
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irq_enable(DT_IRQ_BY_NAME(PTP_INST_NODEID(n), ieee1588_tmr, irq)); \
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} while (0)
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} while (false)
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#define ETH_MCUX_IRQ_PTP(n) \
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COND_CODE_1(DT_NODE_HAS_STATUS(PTP_INST_NODEID(n), okay), \
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@ -69,7 +69,7 @@
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if (U < STATS_PAGE_COUNT_THRESHOLD) { \
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(*(&flash_sim_stats.erase_cycles_unit0 + (U)) += 1); \
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} \
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} while (0)
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} while (false)
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#if (CONFIG_FLASH_SIMULATOR_STAT_PAGE_COUNT > STATS_PAGE_COUNT_THRESHOLD)
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/* Limitation above is caused by used LISTIFY */
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@ -135,7 +135,7 @@ STATS_NAME_END(flash_sim_thresholds);
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#else
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#define ERASE_CYCLES_INC(U) do {} while (0)
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#define ERASE_CYCLES_INC(U) do {} while (false)
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#define FLASH_SIM_STATS_INC(group__, var__)
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#define FLASH_SIM_STATS_INCN(group__, var__, n__)
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#define FLASH_SIM_STATS_INIT_AND_REG(group__, size__, name__)
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@ -307,7 +307,7 @@ static const struct gpio_driver_api gpio_litex_driver_api = {
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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} while (0)
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} while (false)
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#define GPIO_LITEX_INIT(n) \
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static int gpio_litex_port_init_##n(const struct device *dev); \
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@ -512,7 +512,7 @@ do { \
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DT_INST_IRQ_BY_IDX(0, n, priority), \
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gpio_lpc11u6x_isr, &gpio_lpc11u6x_shared, 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(0, n, irq)); \
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} while (0)
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} while (false)
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static int gpio_lpc11u6x_init(const struct device *dev)
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{
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@ -304,7 +304,7 @@ static const struct gpio_driver_api gpio_mcux_driver_api = {
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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} while (0)
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} while (false)
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#define GPIO_PORT_BASE_ADDR(n) DT_REG_ADDR(DT_INST_PHANDLE(n, nxp_kinetis_port))
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@ -384,7 +384,7 @@ static const struct gpio_driver_api mcux_igpio_driver_api = {
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
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} while (0)
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} while (false)
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#define MCUX_IGPIO_INIT(n) \
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MCUX_IGPIO_PIN_DECLARE(n) \
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@ -408,7 +408,7 @@ static const clock_ip_name_t gpio_clock_names[] = GPIO_CLOCKS;
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gpio_mcux_lpc_port_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
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data->isr_list[data->isr_list_idx++] = DT_INST_IRQ_BY_IDX(n, m, irq); \
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} while (0)
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} while (false)
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#define GPIO_MCUX_LPC_IRQ(n, m) \
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COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, m), (GPIO_MCUX_LPC_IRQ_CONNECT(n, m)), ())
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@ -243,7 +243,7 @@ int gpio_sam_init(const struct device *dev)
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gpio_sam_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
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} while (0)
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} while (false)
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#define GPIO_SAM_INIT(n) \
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static void port_##n##_sam_config_func(const struct device *dev);\
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@ -293,7 +293,7 @@ static int i2c_stm32_init(const struct device *dev)
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stm32_i2c_combined_isr, \
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DEVICE_DT_GET(DT_NODELABEL(name)), 0); \
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irq_enable(DT_IRQN(DT_NODELABEL(name))); \
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} while (0)
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} while (false)
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#else
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#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(name) \
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do { \
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@ -310,7 +310,7 @@ static int i2c_stm32_init(const struct device *dev)
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stm32_i2c_error_isr, \
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DEVICE_DT_GET(DT_NODELABEL(name)), 0); \
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irq_enable(DT_IRQ_BY_NAME(DT_NODELABEL(name), error, irq));\
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} while (0)
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} while (false)
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#endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
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#define STM32_I2C_IRQ_HANDLER_DECL(name) \
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@ -780,7 +780,7 @@ static const struct i2c_driver_api i2c_sam0_driver_api = {
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i2c_sam0_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
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} while (0)
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} while (false)
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#if DT_INST_IRQ_HAS_IDX(0, 3)
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#define I2C_SAM0_IRQ_HANDLER(n) \
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@ -67,7 +67,7 @@ int kw41_dbg_idx;
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if (++kw41_dbg_idx == KW41_DBG_TRACE_SIZE) { \
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kw41_dbg_idx = 0; \
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} \
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} while (0)
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} while (false)
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#else
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@ -41,7 +41,7 @@ LOG_MODULE_REGISTER(esp32_intc, CONFIG_LOG_DEFAULT_LEVEL);
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#ifdef CONFIG_INTC_ESP32_DECISIONS_LOG
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# define INTC_LOG(...) LOG_INF(__VA_ARGS__)
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#else
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# define INTC_LOG(...) do {} while (0)
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# define INTC_LOG(...) do {} while (false)
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#endif
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/* Typedef for C-callable interrupt handler function */
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@ -323,7 +323,7 @@ int z_irq_controller_isr_vector_get(void)
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*/
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for (block = 7; likely(block > 0); block--) {
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pReg = x86_read_loapic(LOAPIC_ISR + (block * 0x10));
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if (pReg) {
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if (pReg != 0) {
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return (block * 32) + (find_msb_set(pReg) - 1);
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}
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@ -329,7 +329,7 @@ uint32_t sam0_eic_interrupt_pending(int port)
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DT_INST_IRQ_BY_IDX(0, n, priority), \
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sam0_eic_isr, DEVICE_DT_INST_GET(0), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(0, n, irq)); \
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} while (0)
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} while (false)
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static int sam0_eic_init(const struct device *dev)
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{
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@ -75,7 +75,7 @@ struct ws2812_gpio_cfg {
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DELAY_TxL \
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:: \
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[r] "l" (base), \
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[p] "l" (pin)); } while (0)
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[p] "l" (pin)); } while (false)
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/* Send out a 0 bit's pulse */
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#define ZERO_BIT(base, pin) do { \
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@ -85,7 +85,7 @@ struct ws2812_gpio_cfg {
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DELAY_TxL \
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:: \
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[r] "l" (base), \
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[p] "l" (pin)); } while (0)
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[p] "l" (pin)); } while (false)
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static int send_buf(const struct device *dev, uint8_t *buf, size_t len)
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{
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@ -310,7 +310,7 @@ static const char TIME_STRING_FORMAT[] = "\"yy/MM/dd,hh:mm:ss?zz\"";
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LOG_ERR("%s result:%d", (c), ret); \
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goto error; \
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} \
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} while (0)
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} while (false)
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#define SEND_AT_CMD_IGNORE_ERROR(c) \
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do { \
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@ -318,7 +318,7 @@ static const char TIME_STRING_FORMAT[] = "\"yy/MM/dd,hh:mm:ss?zz\"";
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if (ret < 0) { \
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LOG_ERR("%s result:%d", (c), ret); \
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} \
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} while (0)
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} while (false)
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#define SEND_AT_CMD_EXPECT_OK(c) \
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do { \
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@ -328,7 +328,7 @@ static const char TIME_STRING_FORMAT[] = "\"yy/MM/dd,hh:mm:ss?zz\"";
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LOG_ERR("%s result:%d", (c), ret); \
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goto error; \
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} \
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} while (0)
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} while (false)
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/* Complex has "no_id_resp" set to true because the sending command
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* is the command used to process the response
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@ -341,7 +341,7 @@ static const char TIME_STRING_FORMAT[] = "\"yy/MM/dd,hh:mm:ss?zz\"";
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LOG_ERR("%s result:%d", (c), ret); \
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goto error; \
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} \
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} while (0)
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} while (false)
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NET_BUF_POOL_DEFINE(mdm_recv_pool, CONFIG_MODEM_HL7800_RECV_BUF_CNT,
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CONFIG_MODEM_HL7800_RECV_BUF_SIZE, 0, NULL);
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@ -2982,7 +2982,7 @@ static bool on_cmd_polte_registration(struct net_buf **buf, uint16_t len)
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break;
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}
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parsed = true;
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} while (0);
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} while (false);
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if (parsed && data.user && data.password) {
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data.status = 0;
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@ -3027,7 +3027,7 @@ static bool on_cmd_polte_locate_cmd_rsp(struct net_buf **buf, uint16_t len)
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rsp[out_len] = 0;
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data.status = (uint32_t)strtoul(rsp, NULL, 10);
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} while (0);
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} while (false);
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event_handler(HL7800_EVENT_POLTE_LOCATE_STATUS, &data);
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@ -3124,7 +3124,7 @@ static bool on_cmd_polte_location(struct net_buf **buf, uint16_t len)
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}
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parsed = true;
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} while (0);
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} while (false);
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if (!parsed) {
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LOG_HEXDUMP_ERR(rsp, out_len, "Unable to parse PoLTE location");
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@ -248,7 +248,7 @@ static void enable_msi(pcie_bdf_t bdf,
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mdr = pcie_msi_mdr(irq, vectors);
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mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR);
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if (mcr & PCIE_MSI_MCR_64) {
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if ((mcr & PCIE_MSI_MCR_64) != 0U) {
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pcie_conf_write(bdf, base + PCIE_MSI_MAP1_64, 0U);
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pcie_conf_write(bdf, base + PCIE_MSI_MDR_64, mdr);
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} else {
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@ -60,12 +60,12 @@ uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id)
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uint32_t data;
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data = pcie_conf_read(bdf, PCIE_CONF_CMDSTAT);
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if (data & PCIE_CONF_CMDSTAT_CAPS) {
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if ((data & PCIE_CONF_CMDSTAT_CAPS) != 0U) {
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data = pcie_conf_read(bdf, PCIE_CONF_CAPPTR);
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reg = PCIE_CONF_CAPPTR_FIRST(data);
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}
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while (reg) {
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while (reg != 0U) {
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data = pcie_conf_read(bdf, reg);
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if (PCIE_CONF_CAP_ID(data) == cap_id) {
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@ -83,7 +83,7 @@ uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id)
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unsigned int reg = PCIE_CONF_EXT_CAPPTR; /* Start at end of the PCI configuration space */
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uint32_t data;
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while (reg) {
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while (reg != 0U) {
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data = pcie_conf_read(bdf, reg);
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if (!data || data == 0xffffffffU) {
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return 0;
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@ -510,7 +510,7 @@ static const struct uart_driver_api uart_cc13xx_cc26xx_driver_api = {
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Power_registerNotify(&data->postNotify, \
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PowerCC26XX_AWAKE_STANDBY, \
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postNotifyFxn, (uintptr_t)dev); \
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} while (0)
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} while (false)
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#else
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#define UART_CC13XX_CC26XX_POWER_UART(n) \
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do { \
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@ -541,7 +541,7 @@ static const struct uart_driver_api uart_cc13xx_cc26xx_driver_api = {
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PRCM_DOMAIN_POWER_ON) { \
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continue; \
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} \
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} while (0)
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} while (false)
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#endif
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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@ -560,7 +560,7 @@ static const struct uart_driver_api uart_cc13xx_cc26xx_driver_api = {
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irq_enable(DT_INST_IRQN(n)); \
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/* Causes an initial TX ready INT when TX INT enabled */\
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UARTCharPutNonBlocking(config->reg, '\0'); \
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} while (0)
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} while (false)
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#define UART_CC13XX_CC26XX_INT_FIELDS \
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.callback = NULL, \
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@ -281,7 +281,7 @@ static const struct uart_driver_api mcux_iuart_driver_api = {
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mcux_iuart_isr, DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
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} while (0)
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} while (false)
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#define IUART_MCUX_CONFIG_FUNC(n) \
|
||||
static void mcux_iuart_config_func_##n(const struct device *dev) \
|
||||
{ \
|
||||
|
|
|
@ -1094,7 +1094,7 @@ static const struct uart_driver_api mcux_lpuart_driver_api = {
|
|||
mcux_lpuart_isr, DEVICE_DT_INST_GET(n), 0); \
|
||||
\
|
||||
irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
|
||||
} while (0)
|
||||
} while (false)
|
||||
#define MCUX_LPUART_IRQ_INIT(n) .irq_config_func = mcux_lpuart_config_func_##n,
|
||||
#define MCUX_LPUART_IRQ_DEFINE(n) \
|
||||
static void mcux_lpuart_config_func_##n(const struct device *dev) \
|
||||
|
|
|
@ -2020,7 +2020,7 @@ static int uarte_nrfx_pm_action(const struct device *dev,
|
|||
IRQ_CONNECT(DT_IRQN(UARTE(idx)), DT_IRQ(UARTE(idx), priority), \
|
||||
isr_handler, DEVICE_DT_GET(UARTE(idx)), 0); \
|
||||
irq_enable(DT_IRQN(UARTE(idx))); \
|
||||
} while (0)
|
||||
} while (false)
|
||||
|
||||
#ifdef CONFIG_PINCTRL
|
||||
/* Low power mode is used when disable_rx is not defined or in async mode if
|
||||
|
|
|
@ -1201,7 +1201,7 @@ static const struct uart_driver_api uart_sam0_driver_api = {
|
|||
uart_sam0_isr, \
|
||||
DEVICE_DT_INST_GET(n), 0); \
|
||||
irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
|
||||
} while (0)
|
||||
} while (false)
|
||||
|
||||
#define UART_SAM0_IRQ_HANDLER_DECL(n) \
|
||||
static void uart_sam0_irq_config_##n(const struct device *dev)
|
||||
|
|
|
@ -378,7 +378,7 @@ static const struct uart_driver_api xlnx_uartlite_driver_api = {
|
|||
DEVICE_DT_INST_GET(n), 0); \
|
||||
\
|
||||
irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
|
||||
} while (0)
|
||||
} while (false)
|
||||
#define XLNX_UARTLITE_CONFIG_FUNC(n) \
|
||||
static void xlnx_uartlite_config_func_##n(const struct device *dev) \
|
||||
{ \
|
||||
|
|
|
@ -248,7 +248,7 @@ static const struct spi_driver_api spi_cc13xx_cc26xx_driver_api = {
|
|||
} else { \
|
||||
Power_setDependency(PowerCC26XX_PERIPH_SSI1); \
|
||||
} \
|
||||
} while (0)
|
||||
} while (false)
|
||||
#else
|
||||
#define SPI_CC13XX_CC26XX_POWER_SPI(n) \
|
||||
do { \
|
||||
|
@ -281,7 +281,7 @@ static const struct spi_driver_api spi_cc13xx_cc26xx_driver_api = {
|
|||
PRCM_DOMAIN_POWER_ON) { \
|
||||
continue; \
|
||||
} \
|
||||
} while (0)
|
||||
} while (false)
|
||||
#endif
|
||||
|
||||
#define SPI_CC13XX_CC26XX_DEVICE_INIT(n) \
|
||||
|
|
|
@ -210,7 +210,7 @@ static void usb_sam0_load_padcal(void)
|
|||
DT_INST_IRQ_BY_IDX(0, n, priority), \
|
||||
usb_sam0_isr, 0, 0); \
|
||||
irq_enable(DT_INST_IRQ_BY_IDX(0, n, irq)); \
|
||||
} while (0)
|
||||
} while (false)
|
||||
|
||||
/* Attach by initializing the device */
|
||||
int usb_dc_attach(void)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue