Introduce a function to do the matching job. Add the config for some
platforms to match the mpdir with aff0 only.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Some platforms only use aff0 to match mpdir and GICR.aff. Introduce
GIC_V3_RDIST_MATCHING_AFF0_ONLY to set the matching method only using
aff0. With this config enabled, the matching function will find the
target redistributor by comparing the aff0 only.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Sometimes it is desired for the USB device to detach and reattach itself
to the host. USB device controller driver interface supports detach with
usb_dc_detach() function. Subsequently the device can be reattached to
the bus by calling usb_dc_attach().
USB device stack sets the control transfer callbacks in usb_enable().
Nordic usb_dc_detach() implementation inadvertedly overwrote registered
callbacks with zeroes by clearing endpoint configuration structure. This
lead to a NULL pointer dereference during enumeration after device has
reattached inself to the host.
Preserve the callbacks by removing the eps_ctx_uninit() function.
Endpoints runtime data is initialized in usb_dc_attach() so this should
pose no problems.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The cast for the offset variable will make incorrect register
access when it is over 0x80. Change the char cast to unsigned
char to fix it.
Fixes#49803.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The ADC of the stm32U5 should also waits for the ready Flag
before enabling the peripheral, then wait for the ready Flag
set.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The receive path for the Renesas R-Car CAN controller supports two RX
FIFOs, which are currently configured for standard 11-bit CAN ID data
frames in FIFO0, and extended 29-bit CAN ID data frames in FIFO1.
As this leaves no room for matching remote transmission request (RTR)
frames, have the driver return -ENOTSUP instead of silently accepting RTR
filters.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
In STM32U5 as well it is required to enable VDD before use.
Difference is that U5 enables this under PWR_SVMCR_IO2SV flag.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The usb_dc_sam0 driver is leaking memory when the usb device is detached
using usb_disable().
When a device is detached, the driver does not reliably deallocate the
descriptor bank memory. Therefore, upon the next attach and configure,
another block of memory is allocated. After several connect /
disconnect sequences, the usb interface becomes unresponsive.
This commit adds a static function to release all memory allocated
to the ep descriptors when usb_dc_detach() is called. Since detach is
called from usb_disable(), this releases the memory when the
interface is disabled.
Avoid calling k_free() if buffer pointer is already
set to NULL.
Fixes#49177
Signed-off-by: Steven Slupsky <sslupsky@gmail.com>
... so that the pin keeps the inactive state of the CSN line when it is
not controlled by the QSPI peripheral and the driver is not suspended.
Currently, the nrf_qspi_nor shim deinitializes the nrfx_qspi driver
after each operation, what leaves the pin uncontrolled until a new
operation is requested (and the nrfx_qspi driver is initialized again)
or the driver is suspended (and the pin is put into low-power state).
This can cause the flash chip to needlessly consume current when there
is no pull-up resistor on its CSN line and the line appears active.
Prevent this by keeping the pin in a defined (inactive) state.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commits 9974bb043f
and 00ecc66677.
Add one missing `#ifdef CONFIG_PINCTRL` and remove a no longer needed
one to restore the possibility to use this driver without PINCTRL.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the FSL_FEATURE_MCG_FFCLK_DIV define to decide if we should
call the api to get Fixed Frequency Clock.
This fixes Issue #49924
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Missing include to compile correctly when the
CONFIG_PM && IS_UART_WAKEUP_FROMSTOP_INSTANCE are defined
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add BUILD_ASSERT to check max val of ngpios. If someone sets ngpios to
more than 32, and acts on pin 32 or higher, memory corruption will
result. This is only a problem with the emulator, real hardware
will have limits that are probably much smaller.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
The return values of esp_wifi_set_mode(), and esp_wifi_set_config() were
overwritten once esp_wifi_start() is executed.
This commit fixes that by ORing the return value to the others.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
PR #49550 missed adding proper RTCIO pin mapping
in a few rtcio functions calls, which causes board
to crash. This fixes it.
Closes#50238
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
With the move to start/stop functions the transceiver is not expected
to be enabled after driver initialization.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The USART or LPUART, especially on stm32wl, must set the EXTI
lines corresponding to the wakeUp source.
This LL_EXTI_LINE_xx is given by the Device Tree property.
This makes the system exiting lowpower stop mode on EXTI irq.
The LL_EXTI_LINE_x is exactly the bit(X) set.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix the issue that the initialization will fail when both
CONFIG_SPI_NOR_SFDP_RUNTIME and CONFIG_SPI_NOR_IDLE_IN_DPD are enabled.
The cause of this problem is simply calling the wrong function.
Fixes#33015
Signed-off-by: Xinyang Tan <xinyang.tan@delve.com>
Previously, the lora_send() function would have returned zero regardless
of any error encountered while waiting for the transmit to complete.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Up until now, the Zephyr CAN controller drivers set a default bitrate (or
timing) specified via devicetree and start the CAN controller in their
respective driver initialization functions.
This is fine for CAN nodes using only one fixed bitrate, but if the bitrate
is set by the user (e.g. via a DIP-switch or other HMI which is very
common), the CAN driver will still initialise with the default
bitrate/timing at boot and use this until the application has determined
the requested bitrate/timing and set it using
can_set_bitrate()/can_set_timing().
During this period, the CAN node will potentially destroy valid CAN frames
on the CAN bus (which is using the soon-to-be-set-by-the-application
bitrate) by sending error frames. This causes interruptions to the ongoing
CAN bus traffic when a Zephyr-based CAN node connected to the bus is
(re-)booted.
Instead, require all configuration (setting bitrate, timing, or mode) to
take place when the CAN controller is stopped. This maps nicely to entering
"reset mode" (called "configuration mode" or "freeze mode" for some CAN
controller implementations) when stopping and exiting this mode when
starting the CAN controller.
Fixes: #45304
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This adds a very basic driver to utilize the I3C IP block
on MCUX (e.g. RT685). Note that, for now, this only supports
being the active controller on the bus.
Origin: NXP MCUXpresso SDK
License: BSD 3-Clause
URL: https://github.com/zephyrproject-rtos/hal_nxp
Commit: 2302a1e94f5bc00ce59db4e249b688ad2e959f58
Purpose: Enabling the I3C controller on RT685.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds support for a global workqueue so drivers can defer
IBI callbacks instead of doing it in interrupt context.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This introduces the I3C API for I3C controllers. Currently,
this supports one controller per bus under Zephyr.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Currently, the sdhc_card_busy function is unimplemented in the
SDHC SPI-driver. This causes some functions which rely on f_sync(),
such as fs_close(), to fail as it will timeout the busy-check. This PR
implements sdhc_card_busy by checking if the MISO-line is kept high to
check if the SD-card is idle (not busy).
Solves https://github.com/zephyrproject-rtos/zephyr/issues/49982
Signed-off-by: Ivan Herrera Olivares <ivan.herreraolivares@uantwerpen.be>
1. enable timer5 on dts
2. Replace all BTMR_Type with struct btmr_regs, to make it compatiable
on both mec 15 and 17
3. As MEC15 and MEC17 have different ways to access the register, use
"#if defined" to access counter_cfg->girq_id on different board.
Signed-off-by: Hu Zhenyu <zhenyu.hu@intel.com>
Ensure that the FIFO of each endpoint is initialized during endpoint
configuration, to prevent a NULL FIFO from being encountered during the
first call to usb_dc_ep_write() for a given endpoint.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Add the flash channel support by implementing the controller attached
flash sharing APIs, including flash_read, flash_write, and flash_erase.
For flash_read, the max data payload the module can support is 64 bytes
in one transaction.
For flash_write, the max data payload the module can support is 16
bytes in one transaction.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
DT node "st,stm32f105-pll2-clock" already exists but was not actually used
and PLL2 was not being configured.
PLL2 is available on STM32F105/F107 and should be turned off after turning
off PLL and turned on before turning on PLL again since PLL2 can be
used as a source for PLL. Source for PLL2 is always HSE.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
Fixes an issue with outgoing mcumgr frames that are larger than the
transport MTU size whereby they would wrongly be split up into multiple
frames with multiple start frame headers, which affected SMP over
console transports.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add support to at86rf212[b] sub-giga devices. This work enables use of
pages 0, 2 and 5 in accordance with IEEE-802.15.4/2003/2006/2011. The
proprietary speeds can be object of future work.
Note: It is recommended that user define a power table for better
performance, low emissions and to save power. A reference power table
can be found in the datasheet and should be used for tests only and
not on a final product.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current version of power table is hardcoded in the driver which is a
problem when use devices in production. This change remove all hardcode
from driver and reimplement the feature to allow people create a table
which is defined in devicetree. The big advantage is that each board can
define their own table based on lab tests and allows use of FEM devices
inclusive.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
In old way, gic_rdists[cpu] is calculated via MPIDR_TO_CORE(), but in
real hardware, MPIDR_TO_CORE() isn't a value increment from 0 one by
one, and that will lead gic_rdists[cpu] to point to a wrong address.
GICv3 provides the register GICR_TYPER[1] and it has a field named
Affinity_Value. This field can help to determine where gic_rdists[cpu]
should point.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
1. Move the defines from usb_dc_mcux.h to usb_device_config.h
and fsl_os_abstraction.h. These headers are used by
the SDK USB driver. usb_dc_mcux.h header file is not longer
needed and hence deleted.
2. Delete the Zephyr implementation of the usb_device_struct
driver and use the one implemented inside the SDK USB
driver. This requires updating the references to
usb_device_struct inside the USB driver
3. Move defines and structures used by the driver
out of the header file that is included by the SDK and
into the MCUX USB driver.
4. Use end point defines provided by Zephyr instead of adding
them locally.
5. Add a Kconfig to set the thread stack size
6. Move code to enable interrupts back to usb_attach function.
Interrupts should be enabled after the init is successful,
else we see errors of the ISR getting called before the
init is complete causing Faults
6. Update west.yml to update the NXP HAL to get the updated
SDK USB driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit introduces the 1-wire master driver for maxim ds2485.
The ds2485 master has nearly the same (1-wire) feature set and
i2c-interface as the ds2477.
Therefore the common parts are extracted, but to avoid
any nda troubles only the ds2485 specific part is included.
Compared to older 1-wire masters, the ds2485 supports higher level
commands, supporting multi byte operations, search next, automatic crc
calculation.
In this driver only basic read and write operations are supported,
further hardware features are not yet utilized by the driver.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
