drivers: dai: intel: ssp: add aux data support
Intel SSP configuration can have auxiliary data embedded after it in a variable length tlv array. Enable the parsing of this data and add the data structs to describe the contents. For now add support only for new version 1.5 blob. This is because legacy blob doesn't have size field to describe its variable size. Auxiliary data parsing has currently only 1 setting for link clock needed in ACE platforms. Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This commit is contained in:
Jaska Uimonen
Anas Nashif
parent
c64f91de1a
commit
26e4da9511
3 changed files with 197 additions and 0 deletions
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@ -67,6 +67,62 @@ enum dai_intel_ipc4_connector_node_id_type {
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dai_intel_ipc4_max_connector_node_id_type
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};
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struct ssp_intel_aux_tlv {
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uint32_t type;
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uint32_t size;
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uint32_t val[];
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} __packed;
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struct ssp_intel_mn_ctl {
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uint32_t div_m;
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uint32_t div_n;
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} __packed;
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struct ssp_intel_clk_ctl {
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uint32_t start;
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uint32_t stop;
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} __packed;
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struct ssp_intel_tr_ctl {
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uint32_t sampling_frequency;
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uint32_t bit_depth;
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uint32_t channel_map;
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uint32_t channel_config;
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uint32_t interleaving_style;
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uint32_t format;
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} __packed;
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struct ssp_intel_run_ctl {
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uint32_t enabled;
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} __packed;
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struct ssp_intel_node_ctl {
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uint32_t node_id;
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uint32_t sampling_rate;
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} __packed;
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struct ssp_intel_sync_ctl {
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uint32_t sync_denominator;
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uint32_t count;
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} __packed;
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struct ssp_intel_ext_ctl {
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uint32_t ext_data;
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} __packed;
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struct ssp_intel_link_ctl {
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uint32_t clock_source;
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} __packed;
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#define SSP_MN_DIVIDER_CONTROLS 0
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#define SSP_DMA_CLK_CONTROLS 1
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#define SSP_DMA_TRANSMISSION_START 2
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#define SSP_DMA_TRANSMISSION_STOP 3
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#define SSP_DMA_ALWAYS_RUNNING_MODE 4
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#define SSP_DMA_SYNC_DATA 5
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#define SSP_DMA_CLK_CONTROLS_EXT 6
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#define SSP_LINK_CLK_SOURCE 7
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/**< Base top-level structure of an address of a gateway. */
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/*!
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* The virtual index value, presented on the top level as raw 8 bits,
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@ -1533,6 +1533,143 @@ out:
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return ret;
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}
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static int dai_ssp_check_aux_data(struct ssp_intel_aux_tlv *aux_tlv, int aux_len, int parsed_len)
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{
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struct ssp_intel_sync_ctl *sync;
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int size, size_left;
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switch (aux_tlv->type) {
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case SSP_MN_DIVIDER_CONTROLS:
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size = sizeof(struct ssp_intel_mn_ctl);
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break;
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case SSP_DMA_CLK_CONTROLS:
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size = sizeof(struct ssp_intel_clk_ctl);
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break;
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case SSP_DMA_TRANSMISSION_START:
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case SSP_DMA_TRANSMISSION_STOP:
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size = sizeof(struct ssp_intel_tr_ctl);
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case SSP_DMA_ALWAYS_RUNNING_MODE:
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size = sizeof(struct ssp_intel_run_ctl);
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break;
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case SSP_DMA_SYNC_DATA:
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size = sizeof(struct ssp_intel_sync_ctl);
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sync = (struct ssp_intel_sync_ctl *)&aux_tlv->val;
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size += sync->count * sizeof(struct ssp_intel_node_ctl);
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break;
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case SSP_DMA_CLK_CONTROLS_EXT:
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size = sizeof(struct ssp_intel_ext_ctl);
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break;
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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case SSP_LINK_CLK_SOURCE:
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size = sizeof(struct ssp_intel_link_ctl);
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break;
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#endif
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default:
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LOG_ERR("%s undefined aux data type %u", __func__, aux_tlv->type);
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return -EINVAL;
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}
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/* check for malformed struct, size greater than aux_data or described in tlv */
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size_left = aux_len - parsed_len - sizeof(struct ssp_intel_aux_tlv);
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if (size > size_left || size != aux_tlv->size) {
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LOG_ERR("%s malformed struct, size %d, size_left %d, tlv_size %d", __func__, size,
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size_left, aux_tlv->size);
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return -EINVAL;
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}
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return 0;
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}
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static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_config)
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{
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const struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 *blob = spec_config;
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int aux_tlv_size = sizeof(struct ssp_intel_aux_tlv);
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int hop, i, j, cfg_len, pre_aux_len, aux_len;
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struct ssp_intel_aux_tlv *aux_tlv;
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struct ssp_intel_mn_ctl *mn;
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struct ssp_intel_clk_ctl *clk;
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struct ssp_intel_tr_ctl *tr;
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struct ssp_intel_run_ctl *run;
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struct ssp_intel_node_ctl *node;
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struct ssp_intel_sync_ctl *sync;
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struct ssp_intel_ext_ctl *ext;
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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struct ssp_intel_link_ctl *link;
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#endif
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uint8_t *aux_ptr;
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cfg_len = blob->size;
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pre_aux_len = sizeof(*blob) + blob->i2s_mclk_control.mdivrcnt * sizeof(uint32_t);
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aux_len = cfg_len - pre_aux_len;
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aux_ptr = (uint8_t *)blob + pre_aux_len;
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if (aux_len <= 0)
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return 0;
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for (i = 0; i < aux_len; i += hop) {
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aux_tlv = (struct ssp_intel_aux_tlv *)(aux_ptr);
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if (dai_ssp_check_aux_data(aux_tlv, aux_len, i)) {
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return -EINVAL;
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}
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switch (aux_tlv->type) {
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case SSP_MN_DIVIDER_CONTROLS:
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mn = (struct ssp_intel_mn_ctl *)&aux_tlv->val;
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LOG_INF("%s mn div_m %u, div_n %u", __func__, mn->div_m, mn->div_n);
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break;
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case SSP_DMA_CLK_CONTROLS:
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clk = (struct ssp_intel_clk_ctl *)&aux_tlv->val;
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LOG_INF("%s clk start %u, stop %u", __func__, clk->start, clk->stop);
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break;
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case SSP_DMA_TRANSMISSION_START:
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case SSP_DMA_TRANSMISSION_STOP:
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tr = (struct ssp_intel_tr_ctl *)&aux_tlv->val;
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LOG_INF("%s tr sampling frequency %u, bit_depth %u, channel_map %u,",
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__func__, tr->sampling_frequency, tr->bit_depth, tr->channel_map);
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LOG_INF("channel_config %u, interleaving_style %u, format %u",
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tr->channel_config, tr->interleaving_style, tr->format);
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break;
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case SSP_DMA_ALWAYS_RUNNING_MODE:
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run = (struct ssp_intel_run_ctl *)&aux_tlv->val;
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LOG_INF("%s run enabled %u", __func__, run->enabled);
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break;
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case SSP_DMA_SYNC_DATA:
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sync = (struct ssp_intel_sync_ctl *)&aux_tlv->val;
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LOG_INF("%s sync sync_denominator %u, count %u", __func__,
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sync->sync_denominator, sync->count);
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node = (struct ssp_intel_node_ctl *)((uint8_t *)sync +
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sizeof(struct ssp_intel_sync_ctl));
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for (j = 0; j < sync->count; j++) {
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LOG_INF("%s node node_id %u, sampling_rate %u", __func__,
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node->node_id, node->sampling_rate);
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node++;
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}
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break;
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case SSP_DMA_CLK_CONTROLS_EXT:
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ext = (struct ssp_intel_ext_ctl *)&aux_tlv->val;
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LOG_INF("%s ext ext_data %u", __func__, ext->ext_data);
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break;
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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case SSP_LINK_CLK_SOURCE:
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link = (struct ssp_intel_link_ctl *)&aux_tlv->val;
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sys_write32(sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) |
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I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
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I2SLCTL_OFFSET);
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LOG_INF("%s link clock_source %u", __func__, link->clock_source);
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break;
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#endif
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default:
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LOG_ERR("%s undefined aux data type %u", __func__, aux_tlv->type);
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return -EINVAL;
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}
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hop = aux_tlv->size + aux_tlv_size;
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aux_ptr += hop;
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}
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return 0;
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}
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static int dai_ssp_set_clock_control_ver_1_5(struct dai_intel_ssp *dp,
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const struct dai_intel_ipc4_ssp_mclk_config_2 *cc)
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{
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@ -1620,6 +1757,9 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co
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return 0;
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if (blob15->version == SSP_BLOB_VER_1_5) {
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err = dai_ssp_parse_aux_data(dp, spec_config);
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if (err)
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return err;
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dai_ssp_set_reg_config(dp, cfg, &blob15->i2s_ssp_config);
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err = dai_ssp_set_clock_control_ver_1_5(dp, &blob15->i2s_mclk_control);
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if (err)
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@ -218,6 +218,7 @@
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#define I2SLCTL_OFFSET 0x04
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#define I2SLCTL_SPA(x) BIT(0 + x)
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#define I2SLCTL_CPA(x) BIT(8 + x)
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#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x)
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#define SHIM_CLKCTL 0x78
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#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x)
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