Add driver for Xptek XPT2046 resistive touch controller on SPI.
Only interrupt driven mode supported, does not do polling.
Signed-off-by: Seppo Takalo <seppo.takalo@iki.fi>
esp32_wifi_dev_init() currently starts Wi-Fi stack before
the interface is properly configured, which happens in function
esp32_wifi_init(). This can trigger a ESP32_WIFI_EVENT_STA_START event
before interface initialization, causing a crash.
Moving esp_wifi_start() to esp32_wifi_init() will guarantee that
this won't happen.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Make sure that the interrupt and event routing enable bits have the
reset values in case the Zephyr firmware image is chain-loaded.
When started by MCUboot, these registers values aren't the reset values,
but then Zephyr initializes them in same way. Yet, when the Zephyr
firmware image is chain-loaded by nRF5 bootloader, they may have values
that cause the scheduler to behave in unexpected ways.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
Fix support for GT911 touchscreen driver when not using interrupt.
The controller still requires that the INT pin be set to input in
order to correctly respond to I2C queries.
Also, the GT911 requires that the INT pin is not configured until the
RESET pin has been low at least 10 ms after reset, so add an additional
delay during initialization to account for this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add clock rate definitions for MIPI and LCDIF peripherals, to enable
retrival of these peripheral clock rates at runtime.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for NXP DCNANO LCDIF (lcd interface) peripheral,
present on iMX.RT500. Currently this driver only supports updating
the primary framebuffer, and does not implement support for the cursor
buffer present on this IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for MCUX MIPI DSI 2L. This IP block differs slightly from
the existing MCUX MIPI peripheral, and uses a different hardware
abstraction layer. For these reasons, a new driver was introduced rather
than extending the existing mcux_dsi implementation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of AHB RX buffer allocation. This allows sections
of the AHB RX buffer to be reserved for specific masters, which can
enhance performance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The driver utilizes ST Microelectronics library (which
exists in modules\hal\st\sensor\vl53l1x. Platform specific
headers and source files used by the library are included
and adapted for Zephyr.
The driver can be configured in proj.conf to use a
interrupt/polling methods and the use of the XSHUT pin on
the VL53L1X. All uses were tested successfully.
Signed-off-by: Mark Watson <mwatson@prosaris.ca>
This patch adds watchdog driver for Renesas Smartbond SOCs.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds driver for SmartBond TRNG peripheral that with separate
ISR an thread data pools.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Remove modulus feature and return degrees larger than
count_per_revolution.
This makes it possible to detect if a full rotation has occured.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add support for configuring power on delay when using SPI SDHC. This
allows cards that reliably initialize with a shorter (1ms) delay to
avoid the long initialize delay otherwise imposed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add I2C bus recovery support to the STM32 v1 and v2 driver. The STM32 i2c
peripheral does not natively support I2C bus recovery so recovery is
performed using GPIO bitbanging. This mirrors the bus recovery
implementation for NXP MCUX LPI2C driver.
Fixes: zephyrproject-rtos#54917
Signed-off-by: Maxmillion McLaughlin <github@maxmclau.com>
Allow the uart_console console_out implementation to integrate with
'Device Runtime Power Management'.
Without using runtime PM, it is impossible for the application to manage
the power state of a UART instance, given that any module in the
application could theoretically LOG_* or printk at any point in time.
This removes the need to manually call `pm_device_state_set` when the
lowest power states must be reached, while still allowing console and
printk messages to be output.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Couple issues:
- `sys_clock_set_timeout()` should not base its `mtime` on the current
time either. Tracking the `last_tick` and `last_elapsed` values avoids
the need for all the tick rounding computation.
- The MIN_DELAY thing is pointless. The hardware performs a signed
comparison. If the delay gets close or even behind current time then
the IRQ will be triggered right away. This is unlikely to happen very
often anyway so the constant overhead is uncalled for.
- Runtime 64-bits divisions on 32-bits hardware are very expensive.
- The timer must be enabled before the count can return a sensible
value during driver init (at least on qemu_cortex_a9).
Discussion in PR #54919 applies here too.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The sbs gauge emulator intercepts SMBus messages for an sbs gauge
compatible IC. However, it was incorrectly interpreting the byte order of
received register write values based on the endianness of the SoC
architecture instead of SMBus' defined little-endianness. This fault was
not caught earlier because native posix and the majority of qemu
architectures use little-endian.
Explicitly interpret the write values as little-endian.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Change message to make allow distinguishing between error while
getting page info for disk configuration and page layout
verification.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Description of the bad behaviour before this change:
The arming of the control EP0_OUT endpoint was not kept under
control. It could happen that the EP0_OUT endpoint was left
armed, after the completion of a complete control transfer.
It is clear that the intention was to NOT keep EP0_OUT constantly
armed while idle, because usb_dc_ep_enable() doesn't arm it,
and the intention was for when usb_dc_ep_read() is called to
collect the Setup-Stage 8-byte data, that is when EP0_OUT is armed,
and before this call is performed, the host will keep getting NAKs
for the Data-Stage of the to_device control transfer.
This happens correctly on the first to_device control transfer with
wLength > 0. However, because usb_dc_ep_read_continue() indiscriminately
re-arms all OUT endpoints, in the case of to_device control transfers
with wLength > 0, on the Data-Stage, the endpoint is also re-armed,
which is wrong, because then the endpoint will be left armed after
the control transfer is over.
In this case when a new to_device control transfer starts, the
Data-Stage will be accepted on the first try. This would still
have worked without a failure if the Setup-Stage would have been
processed immediately, but because we process everything in a work
queue at a later time, when the Setup-Stage associated 8-byte data
buffer is read both the Setup-Stage and Data-Stage have arrived.
At the end of handling the Setup-Stage we try to re-arm the EP0_OUT,
which already contains data, thereby corrupting the received length
portion of the buf_ctl register. (Obviously other fields are changed
too, but the length field is the one that first causes chaos, cause
it's written to the maximum, which is 64.) The above mentioned Data-Stage
already has a message in its workqueue for it to be processed, but
it is picked up only after the length field has been corrupted.
Because of this usb_dc_ep_read() thinks there is more data in the buffer
than there really is, and everything becomes de-synchronized, with
later reads accessing uninitialized parts of the buffer.
This sounds like a fundamental failure, that should make it impossible
to operate USB, however the reason this behaviour doesn't make it
impossible to enumerate the device is that this only affects
to_device control transfers with wLength > 0, and during enumeration
there are not many of those happening.
When enumerating a HID keyboard, there is only _one_ of those
happening, and it is the initial setting of the lock light led status.
And that first one succeeds because it's the first one. (However, later
lock light setting control transfers can cause problems, which is how
this problem was encountered.)
The solution in this commit is to keep better control over when EP0_OUT
is armed. This forces the Data-Stage to arrive later (the host will keep
re-trying), and that way the corruption of the buffer control register
is avoided.
Summary of the changes:
- Rework the logic around deciding wether to re-arm the out endpoint
after a read. For non-0 endpoint the previous behaviour is kept,
however for EP0 it is only re-armed if more OUT transactions are
expected for that SETUP transfer (be it data-stage or status-stage)
- Force un-arm the EP0_OUT endpoint in case a stall condition is observed.
- When a setup transfer is received check if EP0_OUT is already armed.
If armed then log a warning message, and force-disarm it.
- When a setup req interrupt fires, don't immediately force the next
read to get it, instead, it will be read only after a setup message
is extracted from the message queue.
- When a setup packet is received abort any unfinished previous control
transfers:
- cancel any data buffers given to the EP0_IN endpoint
- drop any new ep0_in writes that are attempted before this newest
setup packet's associated message is extracted from the message
queue.
- In the ISR, check buffer interrupts before setup req interrupts.
This is to make sure that the final 0-length status message from the
previous setup packet is consumed before the new setup packet.
(this is the only case now when both interrupts could be seen as
having fired by the time the interrupt handler routine executes.
Signed-off-by: Purdea Andrei <andrei@purdea.ro>
Co-authored-by: Johann Fischer
The pwm_mchp_xec driver doesn't clear the divisor or clock select fields
of the config register value before writing it back. If the register
was previously written, the new values were being logically OR'd with
the prior values.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Voltage comparator driver submits notifications into system work queue,
this change will make driver to use dedicated work queue, and priority
of dedicated work queue are configurable as well.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Extends dmamux driver to support DMAMUX 2,
which supports the BDMA on STM32H7 devices.
Co-authored-by: Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Wrap calls to DMA drivers through fops to allow
different dmamuxes to point to different types of
dma with different function calls.
In preperation to add support for BDMA and DMAMUX2.
Co-authored-by: Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
update MEC172x adc driver to support device PM.
Implement pm resume and suspend actions to put adc
pins in proper state for suspend and resume.
Notify kernel of busy when adc sampling is in progress.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Added initial version of Infineon CAT1 GPIO driver.
Added initial version of binding file for Infineon CAT1 GPIO driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 UART driver.
Added initial version of binding file for Infineon CAT1 UART driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add initial version of Infineon CAT1 clock control driver.
- supports clock initialization based on board DT configuration.
Added initial version of system_clocks.dtsi for Infineon PSoC 6 SOC.
Includes: clk_imo, path_mux0..4, fll0, pll0, clk_hf0..4, clk_fast,
clk_slow and clk_peri.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add PLLI2S support within clock_control driver.
This implementation is compatible with "st,stm32f412-plli2s-clock"
binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PLLI2S support within clock_control driver.
This implementation is compatible with "st,stm32f4-plli2s-clock"
binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Polarity support added to XEC PWM driver. This allows (for example) PWM
controlled LEDs that are active low to actually be turned off when set
to off.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Generalize the driver for PCAL6408A into a more abstract base
and reuse this abstraction to implement a driver for
PCAL6416A.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Fixed th02_channel_get() code to return -ENOTSUP when the channel is not
supported.
Fixes#55160.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
