Drops calling the UART FIFO read function during the setup
function (when not in async mode) which could cause issues on
some devices since this function is not called in an ISR.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The parity, stop bits and data bits config was hard-coded instead of
taken from the device tree.
Signed-off-by: Marco Widmer <marco.widmer@bytesatwork.ch>
Increase the SPI RX driver stack size by 128 bytes. Overflows have
previously been observed on real hardware at the default stack size of
512.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The `riscv_plic_irq_enable` & `riscv_plic_irq_disable` are very
similar, refactor them out into `plic_irq_enable_set_state`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Add support of r8a779f0 cpg driver.
r8a779f0 soc has its own clock tree.
Gen4 SoCs common registers addresses have been added in header.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas R-Car Gen4 is different from Gen3 regarding pinmux.
While Gen3 had only one base address to manage all pins,
Gen4 has one set of pinmux registers per GPIO banks.
We could expose one pinmux register per GPIO controllers,
but that would break potential compatibility with Linux
Device tree.
Instead create a reg_base array to parse all reg base from
device tree and identify proper base address based on the pin
definition.
This imply to add a pfc_base parameter to most of the pfc_rcar
function.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas Gen4 SoCs GPIO IPs are using one more
register comparing to Gen3 SoCs.
The new "INEN" register is used to enable general input.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
In the case where a transaction is spilt due to the rx buff len
being longer than the tx or the transaction buffer exceeding the
size of the requested buffer with non gpio CS, the chip select
would be de-asserted/asserted in the middle of the transaction.
Fixes: #57577
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
When CONFIG_IEEE802154_RAW_MODE is set there is no network interface
that could provide pointer to the device the interface is running on top
of. The current implementation of nRF5 ieee802154 driver implicitly
assumes that such an interface is always present, which leads to crashes
when raw mode is enabled.
This commit adds support for IEEE802154_RAW_MODE in nRF5 ieee802154
driver by latching pointer to the ieee802154 device on initialization if
needed so that it doesn't have to be retrieved using the network
interface in run-time.
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Since lsm6dsv16x may be multi-instantiated, triggers must be enabled
and configured on DT basis and not only thru CONFIG_LSM6DSV16X_TRIGGER
macro; if either int1-gpios of int2-gpios (or both) are configured
in DT, the flag trig_enable is set to 'true' for that instance.
The previous implentation was lacking the check of those two Device
Tree properties, so trig_enabled was always true for all instances.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Introduced `CONFIG_PLIC_SHELL` to enable the build of shell
debugging command to get the hit count of each interrupt
controller's IRQ line. This is especially useful when working
with dynamically installed ISRs, which will be the case for
`plic_sw`.
Example usage:
```
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 177
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 236
uart:~$ plic stats clear interrupt-controller@c000000
Cleared stats of interrupt-controller@c000000.
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 90
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Maxim Adelman <imax@meta.com>
if-conditionals should have brackets according to Zephyr's
coding standard, and explicitly compares `edge_irq` against 0.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The WS2812 LED strip driver does not use a scratch byte, therefore
free up a byte per pixel which was unused except in the GPIO-based
driver whereby it is used
Signed-off-by: Jamie McCrae <spam@helper3000.net>
Enable a condition as define dma_callback function only if
any one instance of ns16550 has dmas parameter in dts.
This resolves conflict of dma_callback function defined but
not used warning in case of UART_ASYNC_API enabled but dmas
parameter is not provided to any ns16550 UARTs dts instances.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Removed if (IS_ENABLED()) and used #if as they are causing CI failures
and removed LPSS related functions which are not under LPSS config.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Reference counting was broken when adding the enable delay.
Now reverted to previous pattern.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
This commit adds support for more STM32 CPUs that has
a different DMA interface. This was tested only for
the nucleo_l476rg.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Previously the STM32 DMA driver was dependent on a very specific
name for the DMA in the DTS. This hidden requirement has caused
a bit of confusion. This commit changes the driver to instead
always use the first DMA listed in the ADC node's dma property.
Should fix: #65387
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
These are not needed and are now causing build errors since the
pm_device calls are always there and need the header to become a no-op.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The pm_policy_state_lock_put and pm_policy_state_lock_put functions
already become a no-op if CONFIG_PM is not enabled. Drop the guards
around it in few different drivers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Due to a typo it is not possible to select the main oscillator (MOSC) as a
clock source for an RA Microcontroller. This patch resolves the issue.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
This add regulator driver for Smartbond DA1469X SOC.
Driver can control VDD, V14, V18, V18P, V30 rails,
full voltage range supported by SOC is covered.
For VDD, V14, V18, V18P DCDC can be configured.
Special VDD_CLAMP (always on) and VDD_SLEPP are added
to allow configuration of VDD in sleep modes.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This is called already as soon as the polling thread starts, so the call
in the gpio init function is harmless but redundant, drop it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
When the matrix is connected to consecutive pins on the same port, it's
possible to read the whole row or set the whole column in a single
operation. For the column, this is only possible if the matrix is
configured for driving unselected column, as there's no API to configure
multiple pins at the same time at the moment.
This is more efficient than checking the pins individually, and it's
particularly useful if the row or columns are driven from a GPIO port
expander.
Add some code to detect the condition and enable it automatically as
long as the hw configuration supports it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add an option to drive inactive columns to inactive state rather than
high impedance. This is useful if the matrix has isolation diodes for
every key, as it allows the matrix to stabilize faster and the API for
changing the pin value is more efficient than the one to change the pin
configuration.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Allow enabling the Cortex-m idle timer only if power management is set.
It doesn't make sense to use an idle timer without PM.
It allows adding the idle timer chosen node to dts without enabling the
idle timer by default. Now, the PM config has to be set as well.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Fixes and issue with a variable that has been renamed but whose
reference in the source file has not
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add a Kconfig option to extend the row type to 16 bits, allowing the
library to handle a 16 row matrix.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a typedef for the row type rather than using uint8_t directly, this
allow supporting bigger matrix as an option by using a different type.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Regression failure introduced problem where driver code was not properly
wrapping code that only existed when compiled for IPv4/v6 applications.
Fixes#65549
Signed-off-by: David Leach <david.leach@nxp.com>
On some devices such as STM32U5, there is no UART WKUP dedicated registers
as the hardware block has an integrated autonomous wakeup capability.
Hence it's capable to wake up the device from stop modes (down to Stop 1).
This behavior relies on RCC UESM bit which is enabled by default at reset
and not modified today in drivers.
Since driver will not compile otherwise, remain in this simple
configuration. This might be changed later on, if a need is seen to disable
UESM bit.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This commit fixes the following compiler warnings:
* implicit declaration of function 'strtoul'; did you mean 'strtok'?
* passing argument 2 of 'parse_named_int' discards 'const' qualifier
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Workaround for DMAT errata was applied on all SoCs declaring STM32U5
DMA compatible.
This errata has been fixed in later SoCs revisions and should not be
applied anymore as this can cause compatibility issues with power mgmt
(can not enter STOP1 in some cases).
Declare a specific Kconfig symbol to restrict the workaround only to the
set of SoCs impacted by the issue and requiring workaround.
Note that I preferred using Kconfig over device tree since it doesn't feel
right to declare a compatible on a silicon bug base.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This is an older driver and didn't support the weak
arch_printk_char_out() hook, which is a link-time symbol that allows
logging to work from the first instruction. Some drivers can't do
that because they need an initialization step, but this one works
great.
Signed-off-by: Andy Ross <andyross@google.com>
Serial wakeup feature was only working whe DBG in Stop mode setting
was enabled.
Add required changes to make it functional also when this configuration
isn't set.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
With the introduction of nrfx 3.0.0, values of `nrf_gpio_pin_drive_t`
constants may be defined differently, depending on the SoC family.
Since the nrf-pinctrl.h file is included also from dts files, it is
not possible to use there different definitions of `NRF_GPIO_PIN_*`
values based on Kconfig symbols that indicate given SoC family (as
Kconfig is processed after devicetree) so that those values could
still match `nrf_gpio_pin_drive_t` constants.
To solve this problem, the pinctrl_nrf driver now uses a lookup table
for mapping `NRF_GPIO_PIN_*` indexes to drive configuration values
required by the GPIO HAL.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
So far the driver first changed the configuration of the flash chip
and after that checked the signature of that chip. This could lead
to improper change of the chip configuration if the actually found
one was different than that specified in devicetree.
This commit reverses the order of these two initialization steps and
also restructures a bit the initialization code.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
After integration of nrfx 3.2.0, it is no longer needed to deinitialize
the nrfx_qspi driver to avoid increased power consumption when the QSPI
peripheral is idle. Now it is enough to call `nrfx_qspi_dectivate()`
when a given operation is done. The driver will automatically activate
the QSPI peripheral again when a next operation is requested.
This commit applies the following changes:
- `qspi_device_init` and `qspi_device_uninit` functions are replaced
by `qspi_acquire` and `qspi_release`, respectively; those handle
exclusive access to the QSPI peripheral and deactivation of it or
runtime device power management
- locking is removed from `qspi_send_cmd` as it is the resposibility
of the caller of that function
- `trans_lock` and `trans_unlock` functions are removed together with
the related semaphore as they are no longer needed
- checking of input parameters is moved from `qspi_erase` to its
caller, `qspi_nor_erase`
- `qspi_nor_pm_action` is refactored to properly handle locking of
the QSPI peripheral; checking of the `xip_enabled` flag is removed
from that function as now the call to `pm_device_is_busy()` covers
that (when XIP is enabled, the device is kept indicated as busy)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Consistently use `res` for results of calls to nrfx functions
and `rc` for Zephyr return codes, to avoid mixing up those two
and for example calling `qspi_get_zephyr_ret_code()` for a value
that is already a Zephyr return code. Correct also such call in
`qspi_nor_write()`.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
After entering the Deep Power-down mode, some flash chips ignore all
commands except from the one that releases the chip from the DP mode
and it is not possible to successfully read their Status Register then.
Since the QSPI peripheral tries to read this register when it is being
activated, it consequently fails to send the actual command that would
release the flash chip from the DP mode if that is to be done right
after QSPI initialization.
Prevent this problem by performing the QSPI activation with all pins
disconnected. This causes that the Status Register value is read as
all zeros and allows the activation to always finish successfully,
and the RDPD command to be properly sent.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Those configuration settings should never be part of driver Kconfig file.
Drop them, since they can easily result in Kconfig symbol circular
dependency error.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
