Do not keep both DMA request enabled whenever the SSP is in use. Manage
the SSCR1_TSRE and SSCR1_RSRE bits in sync with the enabled directions.
When only playback is used there is no need to have the RX DMA request
enabled for example.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
The receive FIFO needs to be drained in a different way depending when it
is done.
- before start
If the RX FIFO is in overflow state then we must read all the entries out
to empty it (it was after all full).
- before stop
The DMA might be already running to read out data. Check the FIFO level
change in one sample time which gives us the needed information to decide
to wait for another loop for the DMA burst to finish, wait for the DMA to
start it's burst (DMA request was asserted) or drain the FIFO directly.
No need to drain the RX fifo at probe time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
When loading the SSP configuration from a blob ignore the bits which would
enable the TX/RX or DMA requests at configuration phase.
The TX/RX enable and DMA request is handled by the driver itself. If the
blob wrongly enables any of the bits can have runtime (startup time)
seemingly random issues.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
For the Ambiq Apollo4x soc, every 32 pins share the same IRQ
number. irq_disable() should not be called for the pin interrupt
disablement, otherwise the interrupt of pins in the same GPIO
group will be disabled as well.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Use the "ambiq,gpio" binding to combine the "ambiq,gpio-bank"
child nodes for Apollo4 Plus soc.
Also update the GPIO driver accordingly.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Interupts should be enabled after int line configuration in bmi.
When the device goes to a suspended state interrupts must be disabled.
Signed-off-by: Wojciech Slenska <wsl@trackunit.com>
The wake-up control input is IT8XXX2_IRQ_WU66.
Testing the wake-up functionality on GPF6 is normal.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The NET_L2_ETHERNET_MGMT configuration option is required to allow
setting MAC address or PLCA parameters with the LAN865x driver.
To avoid mistakes with per-board configuration files - it has been moved
to Kconfig and automatically selected when the driver support is enabled.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Handle the situation when OA TC6 compliant device signals to the host
that its configuration is lost - i.e. the SYNC bit in the footer is
cleared.
In this (unlikely happen) situation the device is reset and reconfigured.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
As part of IRQ service routine, there is at least one data transmission
performed between OA TC6 compliant device and HOST uC.
As this transmission can happen when there is no valid data to be read
(and its only purpose is to deassert the interrupt) the DV bit in footer
may be cleared. As this situation is expected with this approach - the
LOG level can be safely lowered from error to debug.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
According to the OPEN Alliance 10Base-T1x standard (point 7.7), it is
mandatory to read at least single data chunk (no matter if received data
is valid or not) to deassert the interrupt in the LAN865x (then the tc6
structure fields are also updated from the footer).
Current approach with reading OA_BUFSTS register was providing the
required information (RCA and TXC), but could cause transmission "stalls"
as this operation (i.e. control, not data transmission) is not causing
deassertion of the interrupt IRQ_N line from OA TC6 compliant device.
With this patch - the transmission is always performed at least once, so
interrupt is always deasserted.
As the functionality of oa_tc6_update_buf_info() - i.e reading value of
RCA and TXC - has been replaced with extracting data from footer, this
function can be safely removed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In a previous change, STM32U5 GPDMA specific behavior was set into a
specific configuration applying only to few devices impacted by a specific
silicon erratum.
As part of this change, dma suspension before dma stop was set to apply
to the specific erratum workaround.
It appears, this was wrong and dma suspension before dma stop should
be done on all devices compatible with stm32u5 dma. This fix re-instantiate
the correct behavior.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Wakeup-source configuration is about configuring registers.
It belongs to uart_stm32_registers_configure().
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Some modems or networks require PAP authentication for successful
LCP handshake. Tested on U-blox SARA-R5 with zephyr,gsm-ppp.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
This renames the I2C 'DCR' mode to 'LVR' as that is the variable it
should be looking at and not the dcr value. This also fixes the get
'lvr' mode argument.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Either switching to CAN_DEVICE_DT_INST_DEFINE with [1] missed
updating mcp251xfd or missed in merge. Fix using function
pointer for init in mcp251xfd.
[1]: https://github.com/zephyrproject-rtos/zephyr/pull/62925
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Configure the sw trigger just after calibration
So the conversion can start on regular channel on the
software control bit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The Transfer Complete flag (TC) is used to check if a transfer is
complete. This mechanism is used before suspending the UART module to
make sure that all data are sent before the suspend procedure.
The UART ISR clears this flag after completion of a async transfer which
causes a hang during UART device suspend setup.
There is just no need to clear this flag in ISR, it is cleared every
time we start a new async transfer.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
In case of boards where REF_CLK signal is not connected
to the GPIO0 by default add the possibility to use
the optional GPIO16/GPIO17 as a REF CLK source.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Simplify and clarify spi_stm32_shift_m by splitting it in
3 smaller functions with clear names.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
In H7, TXP indicates when its FIFO has room for, at least, one
packet. Thus, rename ll_func_tx_is_empty as ll_func_tx_is_not_full,
to be consistent in all platforms.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Avoind calling startMasterTransfer multiple times in a
transaction by moving it to the transceive() function.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
the FIFO Rx need to have a Minimum memory to works
distributed the rest of the ram_size memory between
the different TX FIFOs except the first which is
a control endtype with max data payload of 64 bytes
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Receiving uart messages like: "\r*\n*\n" ('*' is a wildcard here) resulted
in invalid echo and invalid console_getline() output.
For example after receiving "\rabc\nd\n" uart_console_isr() echoes
"\r\nabcd\r\n" (note that "\r\n" before 'd' is missing) and after calling
console_getline() twice we received "" and "abcd".
uart_console_isr() changes single occurences of '\n' and '\r' to "\r\n" and
to avoid outputting "\r\n\r\n" after receiving "\r\n" it keeps track of the
last character. But it was tracking only the control characters not all
characters so in case of inputs like "\r*\n" the '\n' was omitted because
the last tracked character was '\r'.
Its fixed by tracking last character no matter of its type
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Add an option to call an application specific hook when setting the
column to scan. This makes it possible to handle application specific
quirks.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This will allow to init watchdog on HW's supporting different
number of cpus and watchdogs based on runtime arch_num_cpus
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Printing fractionals currently put the sign on integer values on the
fractional part, for example:
longitude : -6.-207483333
Run an extra abs to get rid of the sign there for latitude, longitude
and altitude, compute the sign separately so it works for numbers
between -1 and 0 as well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
While enabling workaround for PAN 58 the PPI driver is used.
This requires the nrfx PPI driver to be enabled thus CONFIG_NRFX_PPI
Kconfig symbol needs to be set.
Jira: NRFX-1616
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
This check has to be done independent of whether RAM is used for buffers
or not and depends on device maximum length property.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Instead of assuming only RAM is accessible by EasyDMA, use the generic
DMA accessible function.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Some targets may not have `NRF_SPIM_HAS_32_MHZ_FREQ` or
`NRF_SPIM_HAS_16_MHZ_FREQ` symbols but have `NRF_SPIM_HAS_PRESCALER`
symbol defined. The symbol informs that target supports 32 MHz and
16 MHz frequencies for SPIM instances.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
The CLOCK HAL header is only needed for nRF5340 SoC. It's used when
user wants to configure SPIM instance to 32 Mbps. The HAL checks
if is running at 128 MHz as only then 32 Mbps is supported.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
NSEC_PER_SEC is an unsigned literal which will promote variable increment
to unsigned for the comparison operation, thus returning -EINVAL for
negative increment values.
For positive increment, -NSEC_PER_SEC becomes a large unsigned value
which will also return -EINVAL.
Fix by casting NSEC_PER_SEC to an int.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The zephyr bluetooth stack expects the controller to know its public
address, if any. At least for BlueNRG, the public address is forgotten with
every reset/power cycle, so there needs to be a way to set it from within
zephyr. This is accomplished using the `Aci_Hal_Write_Config_Data` HCI
command, as described in PM0237.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
"LL only" is not the only config option of potential interest, e.g. the
public address is also important.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
This allows HCI drivers to expose vendor-specific functions to set the
public address.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
