Add macros for converting between Max Packet Size and total payload
length. Allow drivers specify whether endpoint supports high-bandwidth
interrupt and high-bandwidth isochronous transfers.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The received messages are put into the FIFO one by one in the
order, the hardware will return the queue index for current
message. So use the index instead of reading always from 0.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Power off the SD card in `DISK_IOCTL_CTRL_DEINIT`, instead of only
waiting for the card to be idle then doing nothing. This is a safer
state for `DISK_IOCTL_CTRL_DEINIT`, which is documented as preparing the
disk to be removed from the system. It also has the advantage of
lowering power consumption while de-initialized.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Enables open loop operation when initializing into LRA mode. Open loop
operation is enabled by default for ERM mode. This is hard coded for LRA
mode because calibration is currently unsupported.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Adds "vib-overdrive-mv" device tree property to configure the overdrive
clamp at initialization.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Adds support for boot time configuration of the rated voltage at
initialization via "vib-rated-mv" devicetree property.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Adds the default value for the existing properties to the device tree
and fall back on those values at initialization if necessary.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Removes an unused enum defining the DRV2605 power states. This enum is
dead code so it is being removed.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Use the define to send the reset cmd at quad-flash init :
SPI_NOR_CMD_RESET_EN followed by SPI_NOR_CMD_RESET_MEM
when the st,stm32-qspi-nor has the <reset-cmd> property set.
Reports the jedecID correctly.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Install the default delegate for reporting the CAN core clock frequency at
driver instance initialization. This allows using the default clock
configuration when not using ztest.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Disable input buffer full interrupt for 60h/64h and 62h/66 ports by
calling interrupt controller API. The API has barrier mechanism to
ensure that a thread's requirement to disable peripheral interrupt
takes effect before enabling CPU interrupt. Therefore, the disabling
operation does not occur in ISR and results in interrupt 0 symptom.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Add power management support for Apollo3/Apollo3P SPI, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add power management support for Apollo3/Apollo3P I2C, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add power management support for Apollo3/Apollo3P UART, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Config to enable VLAN promiscuous and untagged.
Config to enable SI message interrupt.
Fix the build warning.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Create the set FD mode function because the old
RTD function is updated to static.
Fix the build warning by update the type of buffidx
and u32SysStatus arguments in the callback function
to uint32_t.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Fixing 3 issues:
1. The mask can be wrong if the alarm register is
set to a MAX value because the alarm bit is the
highest in the alarm register. The mask is now
generated by checking the AE_x bits in the time
registers.
2. Fixing possible NULL pointer exception in
alarm_set_time API. timeptr can be set to NULL
with mask 0 in the alarm_set_time function.
The regs variable for the I2C communication
is written with the correct value from timeptr
only when the right bit in the mask is set.
3. rv8263c8_alarm_set_time() now resets the
alarm status.
4. Interrupts are now enabled by using
rv8263c8_alarm_set_time() rather than when
setting an alarm callback.
Signed-off-by: Daniel Kampert <DanielKampert@kampis-elektroecke.de>
Writing directly to Px_DATA_REG modifies pins which are not
indicated by mask, causing gpio_basic_api test to fail.
Use Px_SET_DATA_REG and Px_RESET_DATA_REG to modify only
pins indicated by mask.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
Set pin to input with no resistors selected when it is configured as
GPIO_DISCONNECTED.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
Clear pending interrupts after disabling TRNG to avoid
smartbond_trng_isr getting called with TRNG disabled
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
The gt911 can recognize up to 5 touch points at a time.
Add code to support these multi-touch events.
Signed-off-by: Farah Fliss <farah.fliss@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Tmp114 has an average function, according to the datasheet this is
default disabled. Add attribute to enable this feature.
Signed-off-by: Fredrik Gihl <fgihl@hotmail.com>
Update spi_bitbang_transceive_async function parameter to it match
with correct one that declared in struct
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
This commit addresses an issue where enabling the alarm or update
callbacks unexpectedly disabled the RTC's programmable clock output
during runtime.
The interrupt configuration has been moved to the driver's init
function.
Signed-off-by: Jakub Topic <jakub.topic@anitra.cz>
This includes helper function for pin configuration
and a DT binding for the pinctrl DT node.
There's two important notes to be made regarding this
protocol:
* pinctrl drivers have no subsytem API to implement as opposed
to clock control drivers. Because of this (and the fact that
`pinctrl_configure_pins()` doesn't require a `struct device`
handle) the pinctrl driver consists only of a helper function,
which implements the `PINCTRL_CONFIGURE_PINS` command.
Additionally, the `scmi_protocol` structure is defined inside
the pinctrl helpers source file to avoid redundant code
(otherwise, each SCMI-based pinctrl driver would have to define
it its source file).
* each vendor may have their own set of pin propeties and DT
representations for them. Because of this, there can't be a
generic, SCMI-based pinctrl driver. As such, each vendor who
wants to use the SCMI support for pinctrl operations will have
to implement their pinctrl driver (which, to put it simply,
revolves around implemeting `pinctrl_configure_pins()`) and
make use of the pin configuration function introduced in this
commit. Moreover, this means that each vendor will have control
over the way their pin properties are encoded in the
`scmi_pinctrl_settings` structure.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This includes:
1) Source containing helper functions, each
implementing a command from the clock management
protocol.
2) A clock controller driver making use of said
helper functions and implementing the clock
subsystem API.
3) A DT binding for clock protocol node.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Introduce core support for ARM's SCMI (System Control and
Management Interface). This includes:
* shared memory (SHMEM) driver. This consists of a suite
of functions used to interact with the shared memory area.
* shared memory and doorbell-based transport layer driver.
Data is passed between platform and agent via shared
memory. Signaling is done using polling (PRE_KERNEL) and
doorbells (POST_KERNEL). This makes use of Zephyr MBOX API
(for signaling purposes) and the SHMEM driver (for polling
and data transfer).
* core driver - acts as glue between transport and protocol
layers. Provides synchronized access to transport layer
channels and channel assignment/initialization.
* infrastructure for creating SCMI protocols
This is based on ARM's SCMI Platform Design Document: DEN0056E.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
