drivers: fpga: simplify load mode selection of iCE40
Replace the enum for load modes for the iCE40 with a boolean flag, as there are only two options: - SPI: default, which should be used whenever possible - GPIO bitbang: workarorund, in case a low-end microcontroller is used Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
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3 changed files with 10 additions and 30 deletions
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@ -42,14 +42,7 @@
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* achieve the minimum 1 MHz clock rate for loading the iCE40 bistream. So
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* in order to bitbang on lower-end microcontrollers, we actually require
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* direct register access to the set and clear registers.
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*
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* With that, this driver is left with 2 possible modes of operation which
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* are:
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* - FPGA_ICE40_LOAD_MODE_SPI (for higher-end microcontrollers)
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* - FPGA_ICE40_LOAD_MODE_GPIO (for lower-end microcontrollers)
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*/
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#define FPGA_ICE40_LOAD_MODE_SPI 0
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#define FPGA_ICE40_LOAD_MODE_GPIO 1
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/*
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* Values in Hz, intentionally to be comparable with the spi-max-frequency
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@ -111,7 +104,7 @@ static void fpga_ice40_crc_to_str(uint32_t crc, char *s)
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/*
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* This is a calibrated delay loop used to achieve a 1 MHz SPI_CLK frequency
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* with FPGA_ICE40_LOAD_MODE_GPIO. It is used both in fpga_ice40_send_clocks()
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* with the bitbang mode. It is used both in fpga_ice40_send_clocks()
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* and fpga_ice40_spi_send_data().
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*
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* Calibration is achieved via the mhz_delay_count device tree parameter. See
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@ -573,12 +566,8 @@ static int fpga_ice40_init(const struct device *dev)
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#define FPGA_ICE40_GPIO_PINS(inst, name) (volatile gpio_port_pins_t *)DT_INST_PROP_OR(inst, name, 0)
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#define FPGA_ICE40_LOAD_MODE(inst) DT_INST_PROP(inst, load_mode)
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#define FPGA_ICE40_LOAD_FUNC(inst) \
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(FPGA_ICE40_LOAD_MODE(inst) == FPGA_ICE40_LOAD_MODE_SPI \
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? fpga_ice40_load_spi \
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: (FPGA_ICE40_LOAD_MODE(inst) == FPGA_ICE40_LOAD_MODE_GPIO ? fpga_ice40_load_gpio \
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: NULL))
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(DT_INST_PROP(inst, load_mode_bitbang) ? fpga_ice40_load_gpio : fpga_ice40_load_spi)
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#ifdef CONFIG_PINCTRL
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#define FPGA_ICE40_PINCTRL_CONFIG(inst) .pincfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(inst)),
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@ -589,8 +578,6 @@ static int fpga_ice40_init(const struct device *dev)
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#endif
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#define FPGA_ICE40_DEFINE(inst) \
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BUILD_ASSERT(FPGA_ICE40_LOAD_MODE(inst) == FPGA_ICE40_LOAD_MODE_SPI || \
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FPGA_ICE40_LOAD_MODE(inst) == FPGA_ICE40_LOAD_MODE_GPIO); \
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BUILD_ASSERT(FPGA_ICE40_BUS_FREQ(inst) >= FPGA_ICE40_SPI_HZ_MIN); \
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BUILD_ASSERT(FPGA_ICE40_BUS_FREQ(inst) <= FPGA_ICE40_SPI_HZ_MAX); \
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BUILD_ASSERT(FPGA_ICE40_CONFIG_DELAY_US(inst) >= FPGA_ICE40_CONFIG_DELAY_US_MIN); \
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@ -8,20 +8,14 @@ compatible: "lattice,ice40-fpga"
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include: spi-device.yaml
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properties:
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load-mode:
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type: int
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required: true
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load-mode-bitbang:
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type: boolean
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description: |
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Configure the method used to load the bitstream.
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The bitstream may be loaded via 2 separate methods:
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0 := load the FPGA via SPI transfer
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1 := load the FPGA via bit-banged GPIO
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Option 0 may be suitable for some high-end microcontrollers.
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Option 1 is suitable for low-end microcontrollers. This option
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requires clk-gpios, pico-gpios, gpios-set-reg, and gpios-clear-reg
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to be defined.
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Example usage:
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load-mode = <0>;
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Select the bitbang mode for loading the bitstream into the FPGA.
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This is a workaround to meet the timing requirements fo the iCE40
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on low-end microcontrollers.
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This option requires clk-gpios, pico-gpios, gpios-set-reg, and
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gpios-clear-reg to be defined.
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cdone-gpios:
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type: phandle-array
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required: true
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@ -13,7 +13,7 @@ test_spi_fpga_ice40_gpio: ice40@0 {
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reg = <0>;
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spi-max-frequency = <1000000>;
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load-mode = <0>;
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load-mode-bitbang;
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cdone-gpios = <&test_gpio 0 0>;
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creset-gpios = <&test_gpio 0 0>;
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config-delay-us = <3900>;
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@ -26,7 +26,6 @@ test_spi_fpga_ice40_spi: ice40@1 {
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reg = <1>;
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spi-max-frequency = <1000000>;
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load-mode = <1>;
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cdone-gpios = <&test_gpio 0 0>;
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creset-gpios = <&test_gpio 0 0>;
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clk-gpios = <&test_gpio 0 0>;
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