This commit should deal with updating
the way USBD was handling the DMA
engine. Based on the #73803 request
DMA should be handled via the DMA
driver API class and not directly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
When device was resumed from sleep OUT endpoints were most
likely not enabled due to condition that checked pending transfer.
Configured OUT endpoints should be enabled (ready for RX)
if they were enabled by interfaces.
Now separate bit field enabled is added and check to
see if OUT endpoint should be ready for reception after
sleep is done.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Callback with USB_DC_EP_DATA_OUT was called directly from
interrupt handler (handle_ep0_rx()) while rest of the interrupt
conditions were not checked yet.
Some interfaces started next transfer directly from this callback
resulting in case where TX endpoint was still marked as busy
and transfer was eventually abandoned.
Now message is sent from all affected endpoints after every USB
pending interrupt is handled.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Switching from write to read on EP0 is done when data is
transmitted.
Additionally receiver is enabled when NAK is created in
response to OUT token. This may happen when host sent
ZLP before everything was transmitted.
This case flushed receiver FIFO which could lead to
setup packet corruption.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add support for automatic control of PLL for USB subsystem.
This utilized virtual USB clock present in clock control.
USB driver enables PLL when device is attached or USB
sends resume signaling.
PLL can be turned off (if application does not requested it)
when device is detached (application request)
or USB host sends suspend request.
When VBUS is not present or application did not started USB yet
PD_DOMAIN_SYS is also not acquired that allows for deep
sleep. When USB is active deep sleep will never be activated.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
When EP0 was disabled EP0 was setup to ignore setup and
out packets.
In usb_dc_ep_enable() function mask was never cleared.
It resulted in USB stop functioning after application
disabled endpoint (usb_disable()) and then tried
to enable usb again.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Implement absolute minimum necessary to get Buffer DMA working. Require
Data Cache to be disabled if DWC2 OTG has DMA enabled because the stack
does not currently guarantee cache line alignment for allocated buffers.
Set EPENA bit before disabling IN endpoints because it seems to be
necessary in Buffer DMA mode (without EPENA the wait for INEPNAKEFF does
time out). Setting EPENA should have no impact on Completer mode
operation (where EPENA is not necessary for INEPNAKEFF to trigger).
Programming Guide recommends programming SUPCnt to 3, but the only
advantage would be to be able to tell how many back-to-back SETUP packets
were received if there was no more than 3 back-to-back SETUPs. This
information doesn't seem to be useful. The disadvantage is that the
buffer needed for receiving SETUP packet must be able to hold SUPCnt
multiple of 8 bytes. Use SUPCnt 1 so the 8 bytes buffer is enough.
Make sure to clear StsPhseRcvd interrupt bit in Buffer DMA mode because
the DMA seems to prevent the SETUP Phase Done interrupt from triggering
if StsPhseRcvd is set. Clearing this bit doesn't seem to be necessary in
Completer mode. This bit is set on control transfers with data stage
from host to device.
Both Buffer DMA and Completer mode operation on nRF54H20DK was verified
using USB2CV Chapter 9 Tests and MSC Tests with Mass Storage sample.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Do not use sys_clear_bits() followed by sys_set_bits() on DCTL register
to avoid writing to DCTL register twice - first with zeroed out address,
and then with the new address. Change the code to write the address in
one DCTL register write.
Do not use sys_set_bits() to set test mode, but rather prepare the
correct value first.
Set DCFG and GUSBCFG registers in one go. There is no point in reading
back the value or doing multiple subsequent writes to these registers.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
udc_mcux_ehci is based on the MCUX USB controller driver
(usb_device_ehci.c); udc_mcux_ip3511 is based on the
MCUX USB controller driver (usb_device_lpcip3511.c);
add related Kconfig and CMake; include the usb_phy.h path in
modules/hal_nxp/usb/CMakeLists.txt because udc_mcux.c use it;
add related macros to usb_device_config.h;
update CMakeLists for udc_mcux_ehci and udc_mcux_ip3511.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Add Kconfig option for enabling high speed USB support for the native posix
USB controller driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Release buffer allocated in dwc2_ctrl_feed_dout() on endpoint deactivate
to prevent the buffer from leaking on USB stack disable.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
According to the Zephyr documentation, the number of bytes available
for read should be returned if the input data and length parameters are
NULL and zero, respectively. This commit corrects this behavior.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Since the fifo control register and ready bit are checked in ISR
function, this commit locks IRQ when accessing these registers to
prevent racing conditions.
Tested with: Google spikyrock project
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
This commit addresses some issues during the extended endpoint(ep
number is larger than 4) access. There are enable and ready bits for
each endpoint on the IT82xx2 chip. The transaction completion should be
determined by the ready and enable bits of the corresponding endpoint.
Additioinally, for non-control endpoint, the FIFO control register is
selected before writing data and cleared when the IN transaction is
completed. When an IN token interrupts, the FIFO control register
should be checked if it's selected to prevent fake tokens.
Tested with: Google spikyrock project
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Make sure to feed control OUT endpoint with at least 8 bytes buffer to
make it possible to always receive SETUP data. This solves the assertion
failure in net_buf_add() called inside dwc2_handle_evt_setup() when a
host decides to start new control transfer immediately after it has
issued control transfer with Data Stage from host to device with wLength
less than 8.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add support for GPIO controlled disconnect pullups. This is used in F1
based devices, copied from the legacy driver.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
On nRF54H20DK the USB PHY is powered from VBUS. When the USB cable is
not connected, the PHY is not powered and the PHY clock disappears.
Because the GOUTNAKEFF and INEPNAKEFF can only ever be set when PHY
clock is active, the waits for these bits do timeout if cable is
disconnected. Workaround the issue by aborting the wait if vendor quirk
indicates that PHY clock has abruptly vanished.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add UDC driver for IT82xx2 SoC. This commit passes tests with
1. samples/subsys/usb/cdc_acm/
2. samples/subsys/usb/console/
3. The extend endpoint test with CDC ACM tool
4. USB suspend/resume detection
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Flushing TxFIFO is racing with actual use of the TxFIFO. The software
controls only one side of the race (flush trigger) while the host
controls the other side. Therefore, locking interrupts before flushing
TxFIFO is not protecting against the race condition.
Disable the endpoint on dequeue to make sure that TxFIFO flushing won't
conflict with host actions (because the endpoint would be forced to NAK
the IN tokens before the TxFIFO is flushed).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Do not set NAK bit again for endpoints that already have NAK bit set.
Do not wait for OUT endpoint 0 disable because it cannot be disabled by
application (DOEPCTL0 EPDis bit is Read-Only).
Disable endpoints before disabling interrupts because it is necessary to
handle RXFLVL interrupt (in Slave mode) for GOUTNAKEFF to become active.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
cbprintf_package complains about char usage for %p
string argument and suggests void * usage.
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
DWC2 documentation unfortunately assigns somewhat confusing semantics to
endpoint "enable"/"disable" and "activate"/"deactivate". The Zephyr USB
device stack endpoint enable/disable refers to DWC2 activate/deactivate.
The DWC2 endpoint enable/disable actions can be loosely referred to
Zephyr USB stack enqueue/dequeue.
Rename the functions and rework internal working to match DWC2
Programming Guide. This makes endpoint halt work as expected by the
stack and therefore fixes all classes that rely on correct STALL
handling. Most notable STALL user is the Mass Storage class.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
DWC2 programming guide mentions that SETUP can only be processed by
application after DOEPINTn.SETUP interrupt. Not respecting this
requirement makes setting Global OUT NAK hang while waiting for
GOUTNAKEFF interrupt until the host starts next control transfer.
Global OUT NAK is necessary if the application ever wants to properly
cancel any ongoing transfer.
Change the processing to comply with the programming guide.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
On USBHS, we cannot access the DWC2 register until VBUS is detected and
valid. Kernel event API is used to block if a valid VBUS signal is not
present when the user tries to force usbd_enable().
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The NUMDEVEPS field provides the number of endpoints in addition to the
control endpoint. It is used to iterate over GHWCFG1 register value to
get correct number of configured IN/OUT endpoints. To get it correctly,
we need to use it internally as number including control endpoint.
Interpretation of INEPS misses +1 because value 0 means 1 IN endpoint
and so on.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Although we can get the number of configured OUT and IN endpoints and
endpoint capabilities from the DWC GHWCFGn registers, we need to
configure the number of endpoint configuration structs at build time. On
some platforms, we cannot access the hardware register at pre-init, so
we use the GHWCFGn values from the devicetree to provide endpoint
capabilities. This can be considered a workaround, and we may change the
upper layer internals to avoid it in the future.
Also, add a new vendor quirk to fill in platform-specific controller
capabilities.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Rework and rename vendor quirks to better reflect where they intended to
be called. Number of quirks probably not final and will be trimmed
later.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Move most of the controller initialization to a separate function called
during udc_enable(). This allows us to add support for the platform
where the device controller is only available when VBUS is present and
the PHY is powered.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
udc_init() only initializes and enables the USB regulator. This is
enough to detect VBUS changes, the USB controller is enabled in
udc_enable(). Deinitialization happens correspondingly in reverse order.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
For the simple events, do not check whether the device driver and stack
are marked as initialized. USB device notification will reschedule
delivery if the stack is not yet marked initialized.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Pass DIEPTXF address instead of value to sys_read32() to prevent bus
fault when debug logging is enabled.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
- If the peripheral is OTG_HS with ULPI, enable the OTG_HS ULPI clock
- The constant has a slightly different name on stm32h7
- Otherwise, if the peripheral is OTG_HS:
- Disable the OTG_HS ULPI clock in sleep/low power mode,
- If the peripheral is OTG_HS with PHYC[1], enable the PHYC clock.
- Otherwise, if the peripheral is OTG_FS[2] on stm32h7, also disable the
OTG_FS ULPI clock in sleep mode (in the device/ driver, this is done in
usb_dc_stm32_init()),
[1]: Internal HS PHY in stm32f7x2xx and (some) stm32f730xx
[2]: "OTG_FS" on stm32h7 is really just another OTG_HS peripheral, but
without any way to actually connect a HS PHY
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
DWC USB 2.0 HS OTG Controller sets USB Reset interrupt after Reset
signalling starts, but before the High-Speed Detection Handshake. This
allows software to perform most of the reset handling even before the
connection speed is known. The device controller indicates High-Speed
Detection Handshake result is available in DSTS register by setting
Enumeration Done interrupt.
USB stack expects that the connection speed is known immediately after
UDC_EVT_RESET is submitted. Due to this expectation, it is important to
submit UDC_EVT_RESET only after Enumeration Done interrupt to prevent
the USB stack from reading (and storing) actual device speed before
it is known.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
During a control read transfer host is able to start status stage as
soon as it receives last data packet. The time between last data packet
and status stage can be approximately 1 us at High-Speed and 8 us at
Full-Speed (exact timing depends on host but it is mostly constrained by
bus turnaround time).
With sufficient interrupt latency it is therefore possible that both
IEPINT (raised at end of Data Stage) and RXFLVL (raised at Status Stage)
would be set when dwc2 interrupt handler reads GINTSTS register. When
device is operating at High-Speed, the latency introduced by UART logger
backend is enough to trigger this condition. If the RXFLVL is handled
before IEPINT the stack will trigger "Cannot determine the next stage"
error.
Handle IEPINT before RXFLVL to make the handler immune to increased
interrupt latencies.
Co-authored-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
USB_NATIVE_POSIX dependencies were partially broken for
native_sim as the option was duplicated in the boards
defconfigas.
Let's not define it also in the board Kconfig.defconfig
but instead default it to y in its main definition if
building for either native_posix[//64] or native_sim[//64]
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Mass Storage enumeration failed because udc_stm32_ep_mem_config() was only
increasing priv->occupied_mem on endpoint enable, and not decreasing it on
endpoint disable. Fix the issue by decreasing priv->occupied_mem
on endpoint disable.
Signed-off-by: Arne Bohnsack <arne.bohnsack@draeger.com>
Updates the linker script fragments under 'drivers' to use
Z_LINK_ITERABLE_SUBALIGN for the subalignment instead of
a hardcoded value of 4.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Submit USBFSOTG_EVT_XFER on halt clear to allow queued
transfers to execute as soon as endpoint STALL is cleared.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
When running the cdc_acm demo on a board with an external ULPI
phy, the device is unable to enumerate:
usb 1-1.8.3.1: new full-speed USB device number 51 using ehci-pci
usb 1-1.8.3.1: device descriptor read/64, error -32
usb 1-1.8.3.1: device descriptor read/64, error -32
the console shows:
[00:00:00.001,000] cdc_acm_echo: Wait for DTR
[00:00:00.007,000] usb_cdc_acm: Device suspended
[00:00:00.902,000] usb_cdc_acm: Device resumed
[00:00:00.902,000] usb_cdc_acm: from suspend
[00:00:25.526,000] usb_cdc_acm: Device suspended
By not disabling the ULPI clock in low power, the usb enumeration
is working and we can run the cdc_acm demo. While touching
this code, add some comments to clarify the macro nesting.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Magic constants throughout the code made this difficult to reason about,
especially with two different units of measurement (bytes and words) at
play.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
