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drivers: udc_dwc2: Add missing register bit defines

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Add missing GINTSTS, GRXSTSR and DEPCTL bit defines based on nRF54H20
register map.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
This commit is contained in:
Tomasz Moń 2024-05-14 07:38:48 +02:00 • committed by Carles Cufí
commit fa912f4389
1 changed files with 56 additions and 0 deletions
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56
drivers/usb/common/usb_dwc2_hw.h
View file

@ -190,32 +190,81 @@ USB_DWC2_SET_FIELD_DEFINE(grstctl_txfnum, GRSTCTL_TXFNUM)
#define USB_DWC2_GINTMSK 0x0018UL
#define USB_DWC2_GINTSTS_WKUPINT_POS 31UL
#define USB_DWC2_GINTSTS_WKUPINT BIT(USB_DWC2_GINTSTS_WKUPINT_POS)
#define USB_DWC2_GINTSTS_SESSREQINT_POS 30UL
#define USB_DWC2_GINTSTS_SESSREQINT BIT(USB_DWC2_GINTSTS_SESSREQINT_POS)
#define USB_DWC2_GINTSTS_DISCONNINT_POS 29UL
#define USB_DWC2_GINTSTS_DISCONNINT BIT(USB_DWC2_GINTSTS_DISCONNINT_POS)
#define USB_DWC2_GINTSTS_CONIDSTSCHNG_POS 28UL
#define USB_DWC2_GINTSTS_CONIDSTSCHNG BIT(USB_DWC2_GINTSTS_CONIDSTSCHNG_POS)
#define USB_DWC2_GINTSTS_LPM_INT_POS 27UL
#define USB_DWC2_GINTSTS_LPM_INT BIT(USB_DWC2_GINTSTS_LPM_INT_POS)
#define USB_DWC2_GINTSTS_HCHINT_POS 25UL
#define USB_DWC2_GINTSTS_HCHINT BIT(USB_DWC2_GINTSTS_HCHINT_POS)
#define USB_DWC2_GINTSTS_PRTINT_POS 24UL
#define USB_DWC2_GINTSTS_PRTINT BIT(USB_DWC2_GINTSTS_PRTINT_POS)
#define USB_DWC2_GINTSTS_RESETDET_POS 23UL
#define USB_DWC2_GINTSTS_RESETDET BIT(USB_DWC2_GINTSTS_RESETDET_POS)
#define USB_DWC2_GINTSTS_FETSUSP_POS 22UL
#define USB_DWC2_GINTSTS_FETSUSP BIT(USB_DWC2_GINTSTS_FETSUSP_POS)
#define USB_DWC2_GINTSTS_INCOMPIP_POS 21UL
#define USB_DWC2_GINTSTS_INCOMPIP BIT(USB_DWC2_GINTSTS_INCOMPIP_POS)
#define USB_DWC2_GINTSTS_INCOMPISOIN_POS 20UL
#define USB_DWC2_GINTSTS_INCOMPISOIN BIT(USB_DWC2_GINTSTS_INCOMPISOIN_POS)
#define USB_DWC2_GINTSTS_OEPINT_POS 19UL
#define USB_DWC2_GINTSTS_OEPINT BIT(USB_DWC2_GINTSTS_OEPINT_POS)
#define USB_DWC2_GINTSTS_IEPINT_POS 18UL
#define USB_DWC2_GINTSTS_IEPINT BIT(USB_DWC2_GINTSTS_IEPINT_POS)
#define USB_DWC2_GINTSTS_EPMIS_POS 17UL
#define USB_DWC2_GINTSTS_EPMIS BIT(USB_DWC2_GINTSTS_EPMIS_POS)
#define USB_DWC2_GINTSTS_RSTRDONEINT_POS 16UL
#define USB_DWC2_GINTSTS_RSTRDONEINT BIT(USB_DWC2_GINTSTS_RSTRDONEINT_POS)
#define USB_DWC2_GINTSTS_EOPF_POS 15UL
#define USB_DWC2_GINTSTS_EOPF BIT(USB_DWC2_GINTSTS_EOPF_POS)
#define USB_DWC2_GINTSTS_ISOOUTDROP_POS 14UL
#define USB_DWC2_GINTSTS_ISOOUTDROP BIT(USB_DWC2_GINTSTS_ISOOUTDROP_POS)
#define USB_DWC2_GINTSTS_ENUMDONE_POS 13UL
#define USB_DWC2_GINTSTS_ENUMDONE BIT(USB_DWC2_GINTSTS_ENUMDONE_POS)
#define USB_DWC2_GINTSTS_USBRST_POS 12UL
#define USB_DWC2_GINTSTS_USBRST BIT(USB_DWC2_GINTSTS_USBRST_POS)
#define USB_DWC2_GINTSTS_USBSUSP_POS 11UL
#define USB_DWC2_GINTSTS_USBSUSP BIT(USB_DWC2_GINTSTS_USBSUSP_POS)
#define USB_DWC2_GINTSTS_ERLYSUSP_POS 10UL
#define USB_DWC2_GINTSTS_ERLYSUSP BIT(USB_DWC2_GINTSTS_ERLYSUSP_POS)
#define USB_DWC2_GINTSTS_GOUTNAKEFF_POS 7UL
#define USB_DWC2_GINTSTS_GOUTNAKEFF BIT(USB_DWC2_GINTSTS_GOUTNAKEFF_POS)
#define USB_DWC2_GINTSTS_GINNAKEFF_POS 6UL
#define USB_DWC2_GINTSTS_GINNAKEFF BIT(USB_DWC2_GINTSTS_GINNAKEFF_POS)
#define USB_DWC2_GINTSTS_NPTXFEMP_POS 5UL
#define USB_DWC2_GINTSTS_NPTXFEMP BIT(USB_DWC2_GINTSTS_NPTXFEMP_POS)
#define USB_DWC2_GINTSTS_RXFLVL_POS 4UL
#define USB_DWC2_GINTSTS_RXFLVL BIT(USB_DWC2_GINTSTS_RXFLVL_POS)
#define USB_DWC2_GINTSTS_SOF_POS 3UL
#define USB_DWC2_GINTSTS_SOF BIT(USB_DWC2_GINTSTS_SOF_POS)
#define USB_DWC2_GINTSTS_OTGINT_POS 2UL
#define USB_DWC2_GINTSTS_OTGINT BIT(USB_DWC2_GINTSTS_OTGINT_POS)
#define USB_DWC2_GINTSTS_MODEMIS_POS 1UL
#define USB_DWC2_GINTSTS_MODEMIS BIT(USB_DWC2_GINTSTS_MODEMIS_POS)
#define USB_DWC2_GINTSTS_CURMOD_POS 0UL
#define USB_DWC2_GINTSTS_CURMOD BIT(USB_DWC2_GINTSTS_CURMOD_POS)
/* Status read and pop registers */
#define USB_DWC2_GRXSTSR 0x001CUL
#define USB_DWC2_GRXSTSP 0x0020UL
#define USB_DWC2_GRXSTSR_FN_POS 21UL
#define USB_DWC2_GRXSTSR_FN_MASK (0xFUL << USB_DWC2_GRXSTSR_FN_POS)
#define USB_DWC2_GRXSTSR_PKTSTS_POS 17UL
#define USB_DWC2_GRXSTSR_PKTSTS_MASK (0xFUL << USB_DWC2_GRXSTSR_PKTSTS_POS)
#define USB_DWC2_GRXSTSR_PKTSTS_GLOBAL_OUT_NAK 1
#define USB_DWC2_GRXSTSR_PKTSTS_OUT_DATA 2
#define USB_DWC2_GRXSTSR_PKTSTS_OUT_DATA_DONE 3
#define USB_DWC2_GRXSTSR_PKTSTS_SETUP_DONE 4
#define USB_DWC2_GRXSTSR_PKTSTS_SETUP 6
#define USB_DWC2_GRXSTSR_DPID_POS 15UL
#define USB_DWC2_GRXSTSR_DPID_MASK (0x3UL << USB_DWC2_GRXSTSR_DPID_POS)
#define USB_DWC2_GRXSTSR_DPID_DATA0 0
#define USB_DWC2_GRXSTSR_DPID_DATA2 1
#define USB_DWC2_GRXSTSR_DPID_DATA1 2
#define USB_DWC2_GRXSTSR_DPID_MDATA 3
#define USB_DWC2_GRXSTSR_BCNT_POS 4UL
#define USB_DWC2_GRXSTSR_BCNT_MASK (0x000007FFUL << USB_DWC2_GRXSTSR_BCNT_POS)
#define USB_DWC2_GRXSTSR_EPNUM_POS 0UL
@ -223,6 +272,7 @@ USB_DWC2_SET_FIELD_DEFINE(grstctl_txfnum, GRSTCTL_TXFNUM)
#define USB_DWC2_GRXSTSR_CHNUM_POS 0UL
#define USB_DWC2_GRXSTSR_CHNUM_MASK 0x0000000FUL
USB_DWC2_GET_FIELD_DEFINE(grxstsp_fn, GRXSTSR_FN)
USB_DWC2_GET_FIELD_DEFINE(grxstsp_pktsts, GRXSTSR_PKTSTS)
USB_DWC2_GET_FIELD_DEFINE(grxstsp_bcnt, GRXSTSR_BCNT)
USB_DWC2_GET_FIELD_DEFINE(grxstsp_epnum, GRXSTSR_EPNUM)
@ -456,6 +506,8 @@ USB_DWC2_GET_FIELD_DEFINE(dsts_enumspd, DSTS_ENUMSPD)
#define USB_DWC2_DEPCTL_EPENA BIT(USB_DWC2_DEPCTL_EPENA_POS)
#define USB_DWC2_DEPCTL_EPDIS_POS 30UL
#define USB_DWC2_DEPCTL_EPDIS BIT(USB_DWC2_DEPCTL_EPDIS_POS)
#define USB_DWC2_DEPCTL_SETD1PID_POS 29UL
#define USB_DWC2_DEPCTL_SETD1PID BIT(USB_DWC2_DEPCTL_SETD1PID_POS)
#define USB_DWC2_DEPCTL_SETD0PID_POS 28UL
#define USB_DWC2_DEPCTL_SETD0PID BIT(USB_DWC2_DEPCTL_SETD0PID_POS)
#define USB_DWC2_DEPCTL_SNAK_POS 27UL
@ -472,6 +524,10 @@ USB_DWC2_GET_FIELD_DEFINE(dsts_enumspd, DSTS_ENUMSPD)
#define USB_DWC2_DEPCTL_EPTYPE_BULK 2
#define USB_DWC2_DEPCTL_EPTYPE_ISO 1
#define USB_DWC2_DEPCTL_EPTYPE_CONTROL 0
#define USB_DWC2_DEPCTL_NAKSTS_POS 17UL
#define USB_DWC2_DEPCTL_NAKSTS BIT(USB_DWC2_DEPCTL_NAKSTS_POS)
#define USB_DWC2_DEPCTL_DPID_POS 16UL
#define USB_DWC2_DEPCTL_DPID BIT(USB_DWC2_DEPCTL_DPID_POS)
#define USB_DWC2_DEPCTL_USBACTEP_POS 15UL
#define USB_DWC2_DEPCTL_USBACTEP BIT(USB_DWC2_DEPCTL_USBACTEP_POS)
#define USB_DWC2_DEPCTL0_MPS_POS 0UL