Do not allow enqueuing buffers on endpoints that were not enabled. Doing
so can lead to division by zero later on because the max packet size can
be 0 in disabled endpoint configuration.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Introduce new binding "st,stm32u5-otghs-phy" for OTG_HS PHY. This allows to
configure clock source and handle STM32U5 specific OTG_HS PHY behavior in
driver implementation in a more readable way.
Move OTG_HS PHY clock selection (previously <&rcc STM32_SRC_HSI48
ICKLK_SEL(0)>) from OTG_HS node to OTG_HS PHY node.
Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5
CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
Support enabling OTG_HS PHY clock, which is bit 15 (OTGHSPHYEN) in
RCC_AHB2ENR1. Change OTG_HS clock to be bit 14 (OTGEN).
Calculate in runtime OTG_HS PHY clock source frequency. Try to match that
to supported (16, 19.2, 20, 24, 26, 32 MHz) frequencies and select proper
option with HAL_SYSCFG_SetOTGPHYReferenceClockSelection() API (instead of
hardcoded 16 MHz selection).
Co-authored-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Endpoint disable function is racing against bus traffic. If the bus
traffic leads to transfer completion immediately before the endpoint
disable is executed, then the transfer complete interrupt will remain
set when the endpoint is disabled. For OUT endpoints this leads to "No
buffer for ep" errors, while for IN endpoint this can lead to double
buffer pull which causes assertion failure.
The proper solution would be to change endpoint disable to not actually
wait for the individual events (and accept that the endpoint may not
need to be disabled because the transfer can just finish). For the time
being workaround the issue by clearing XferCompl bit on endpoint
disable.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
When handling incomplete iso IN interrupt mark current transfer as
complete and program the endpoint with any subsequently queued packet.
Program the endpoint directly in interrupt handler because the data
must be programmed before SOF (by the time incomplete iso IN interrupt
is raised there is less than 20% * 125 us = 25 us before SOF).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The NAKSts bit may be set on isochronous OUT endpoints when incomplete
ISO OUT interrupt is raised. The code would then assume that endpoint is
already disabled and would not perform the endpoint disable procedure.
This in turn was essentially halting any transmission on the isochronous
endpoint, abruptly terminating the data stream.
Fix the issue by always following full endpoint disable procedure on
isochronous endpoints.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Ambiq USB HAL do not expect endpoint transaction request when an
endpoint is stalled. This commit addresses this behavior in shim driver
by checking for endpoint's stall status when enqueue request is
received, and defer it until endpoint stall is cleared.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
Accessing DWC2 otg core registers before the clock starts results in
complete system hang. Add a 1 us busy wait to make sure that software
won't access registers before the clock is started.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
DMA transfers do not execute when the USBD peripheral is in Low Power
mode. Make sure that there is no DMA active transfer when entering Low
Power mode and that new DMA transfers are not started when in Low Power
mode because the transfer won't ever finish.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Low Power mode can only be entered when there are no active DMA
transfers. Move the Suspend and Resume processing to thread to allow
waiting for the DMA available semaphore in USB Suspend handler.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The `Kconfig.defconfig` is not good place for put `select PINCTRL`.
Drop `select PINCTL` from `Kconfig.defconfig` and add it at each
driver's Kconfig.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
To remove CONFIG_PINCTRL from board side for numaker boards.
The Drivers using Pinctrl should be turning Pinctrl on
instead of the responsibility of the board.
Fixes#78619
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
USBD peripheral automatically handles Set Address command which can
lead to state mismatch between USB stack and the host. Keep track of
device address and issue fake Set Address commands on mismatch.
This fixes default vs addressed state mismatch that can occur due to
sufficently high SETUP handling latency. The state mismatch was most
commonly seen as SET CONFIGURATION failure when the enumeration happened
during periods with increased latency.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Any request 5 did set the address even if it's a non standard
request like vendor specific requests.
Signed-off-by: David Schneider <schneidav81@gmail.com>
In GCC 14.2.0, the keyvariable in usb_dc_ep_write is detected to be used
before initialization, even though this usage should be safe.
Fix by initializing the key variable to 0, and making the 2 if
statements explicitly checking the same value.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
If the direction of the last setup packet is not to the device but to
the host, then the transfer is not a status stage and should be queued.
This is not checked and prevents a zero length control IN transfer to
the host, e.g. used by the DFU class to indicate the end of the upload
process.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Reset control endpoint busy flags if configured and enabled, otherwise
it could mark the wrong buffer as busy after endpoint disable/enable.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This Kconfig has wrongly been added to defconfig files. It is not the
right place for it. It has never been the right place for it. Drivers
that need it should select the symbol in their Kconfig entries. Drop
PINCTL from Kconfig.defconfig and add proper select at Kconfig.sam*.
Fixes#78619
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some NXP socs with Kinetis USB do not have USB voltage regulator.
It causes build error in USB samples.
Fix it by enabling and disabling the voltage regulator only if
present.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
DWC2 peripherals can have TxFIFO sizes configured to any value between
16 and 32768. The value configured during synthesis is the maximum value
the software can program. Designs that give full flexibility configure
the TxFIFO sizes to value equal to total SPRAM size.
Currently DWC2 driver does not have prior knowledge about the endpoints
used within available configurations and has to come up with TxFIFO0
value up front. The original approach was to use MAX(16, max allowed).
locations. Because DWC2 peripheral cannot have TxFIFO0 with size lower
than 16 locations, always the max allowed was used. This logic prevented
any IN endpoint other than EP0 on designs that have TxFIFO0 size set to
total SPRAM size.
Change the logic to MIN(2 * 16, max allowed) to have sufficient memory
available on flexible designs and allow simultaneous operation if
possible (i.e. when maximum TxFIFO0 size is at least 32).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
DWC2 otg OUT transfers are being used for SETUP DATA0, OUT Data Stage
packets and OUT Status Stage ZLP. On High-Speed it is possible for IN
Data Stage, OUT Status Stage ZLP and subsequent SETUP DATA0 to happen
in very quick succession, making all the three events appear at the same
time to the handler thread.
The handler thread is picking up next endpoint to handle based on the
least significant bit set. When OUT endpoints were on bits 0-15 and IN
endpoints were on bits 16-31, the least significant bit policy favored
OUT endpoints over IN endpoints. This caused problems in Completer mode
(but suprisingly not in Buffer DMA mode) that lead to incorrect control
transfer handling.
The choice between least significant bit first or most significant bit
first is arbitrary. Switching from least to most significant bit first
would have resolved the issue. It would also favor higher numbered
endpoints over lower numbered endpoints.
Swap the order of endpoints in bitmaps to have IN on bits 0-15 and OUT
on bits 16-31 to keep handling lower numbered endpoints first and
resolve the control transfer handling in Completer mode.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
There is an issue where OUT data is not handled correctly when the
toatl length exceeds the MPS. This update fixes the control handling
for the OUT endpoint.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The ready bit is automatically cleared by hardware. When setting other
bits, there is a chance that the ready bit hasn't been cleared yet,
leading to unexpected USB transactions. This commit addresses this
isuue and locks irq for critical section to prevent racing condition.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The IT82xx2 chip has three FIFOs shared across endpoint 1 to 15, and
the FIFO control register is configured based on the active endpoints.
However, there are some issues with FIFO control.
Firstly, when a TRANS_DONE interrupt occurs, the completion of the
transaction should be determined by the ready and enable bits of the
corresponding endpoint. Additionally, only one non-control IN endpoint
can access the IN FIFO at a time. The FIFO control register is selected
before writing data and cleared after the IN transaction is completed.
For OUT endpoints, all endpoint bits must be selected in the OUT FIFO
control register when the endpoint is enabled. This can result in fake
OUT tokens being detected if an interrupt is triggered by another FIFO.
To prevent this, an atomic out_fifo_state variable has been introduced
to handle the detection of fake OUT tokens.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
As per USB 2.0 specification 7.1.5.1: The voltage source on the pull-up
resistor must be derived from or controlled by the power supplied on the
USB cable such that when VBUS is removed, the pull-up resistor does not
supply current on the data line to which it is attached.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
Adds CONFIG_UDC_DWC2_USBHS_VBUS_READY_TIMEOUT_MS that allows
for waiting for a USBHS VBUS ready event for a specified
amount of time. Earlier it waited forever and because of that,
the udc_enable() was blocked forever if the USB cable was
disconnected. Now the function returns error on timeout.
Signed-off-by: Aleksander Strzebonski <aleksander.strzebonski@nordicsemi.no>
The Drivers using Pinctrl should be turning Pinctrl on
this should not be the responsibility of the board. This
commit removes CONFIG_PINCTRL from the boards side for nxp boards.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Peripherals are required to support the suspend state whenever VBUS
is powered, even if bus reset has not occurred (Mandate: Required,
Effective Date: February, 2010).
Remove the stale suspend check that essentially prevented the device
from hibernating when connected to already suspended bus.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Use the quirk to keep only the necessary clocks running when the core is
hibernated. The quirk is necessary to bring the USB suspend current
below the USB 2.0 suspend current limit.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Make it possible to have vendor quirks after hibernation entry sequence
and before hibernation exit sequence.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The suspended flag is checked during SOF and RESUME interrupts, and it
is modified within a delayable work item. To prevent race conditions,
this update ensures that interrupts are disabled (locking IRQs) before
modifying the suspended flag. Additionally, the RESUME interrupt is
enabled only when the USB is suspended.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
According to USB 2.0 Specification the remote wakeup device must hold
the resume signaling for at least 1 ms but for no more than 15 ms. The
DWC2 otg controller requires the software to drive the remote wakeup
signalling for appropriate duration (when LPM is disabled, which is
currently always the case in udc_dwc2). Arbitrarily choose to drive the
resume signalling for 2 ms to have sufficient margin in both directions.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The PMU is not reset by core reset and therefore it is necessary to exit
hibernation on DWC2 disable to prevent endless PMU interrupt loop when
the driver is enabled again.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Enter hibernation in thread context with the lock held to make sure to
not queue any transfers when the core is hibernated.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
UDC API handlers and DWC2 driver thread share not only software
constructs, but also the underlying hardware. Ensure that any UDC API
call is not preempted by DWC2 driver thread (and vice versa) by
acquiring the lock in thread handler.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
When the queue is full, all messages posted inside interrupt handlers
are simply dropped. This problem can be remedied by having the message
queue large enough, but determining the maximum number of messages that
can ever be posted in the system is really complex task.
Hopefully in DWC2 driver there is finite number of events that have to
be processed inside thread handler. Therefore it is unnecessary to
determine the maximum queue size for the events if the events are posted
to k_event object instead of send to k_msgq object.
Use combination of three k_event structures to handle all possible event
sources. This not only guarantees by design that no event will be lost,
but also slightly reduces the memory usage.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Do not allocate TxFIFO in a way that could corrupt Endpoint Information
Controller data (stored at DFIFO Depth address) or access locations
outside the SPRAM.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
For code clarity, this commit adjusts the use of `return` statements
in functions with a void return type as follows:
- Transform `return foo();` into separate statements:
`foo();`
`return;`
- Remove unnecessary `return` statements when
they don't affect control flow.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Do not schedule isochronous data on current frame. While doing so can
work at Full-Speed, it is pretty much impossible to do it quickly enough
at High-Speed.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
