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drivers: udc_dwc2: Add missing GHWCFG bit defines

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Add missing GHWCFG2 and GHWCFG3 defines based on nRF54H20 registers
documentation.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
This commit is contained in:
Tomasz Moń 2024-09-12 12:09:45 +02:00 • committed by Fabio Baltieri
commit 68b8818e02
1 changed files with 35 additions and 0 deletions
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35
drivers/usb/common/usb_dwc2_hw.h
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@ -350,8 +350,27 @@ USB_DWC2_GET_FIELD_AND_IDX_DEFINE(ghwcfg1_epdir, GHWCFG1_EPDIR)
/* GHWCFG2 register */
#define USB_DWC2_GHWCFG2 0x0048UL
#define USB_DWC2_GHWCFG2_TKNQDEPTH_POS 26UL
#define USB_DWC2_GHWCFG2_TKNQDEPTH_MASK (0x1FUL << USB_DWC2_GHWCFG2_TKNQDEPTH_POS)
#define USB_DWC2_GHWCFG2_PTXQDEPTH_POS 24UL
#define USB_DWC2_GHWCFG2_PTXQDEPTH_MASK (0x3UL << USB_DWC2_GHWCFG2_PTXQDEPTH_POS)
#define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE16 3
#define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE8 2
#define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE4 1
#define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE2 0
#define USB_DWC2_GHWCFG2_NPTXQDEPTH_POS 22UL
#define USB_DWC2_GHWCFG2_NPTXQDEPTH_MASK (0x3UL << USB_DWC2_GHWCFG2_NPTXQDEPTH_POS)
#define USB_DWC2_GHWCFG2_NPTXQDEPTH_EIGHT 2
#define USB_DWC2_GHWCFG2_NPTXQDEPTH_FOUR 1
#define USB_DWC2_GHWCFG2_NPTXQDEPTH_TWO 0
#define USB_DWC2_GHWCFG2_MULTIPROCINTRPT_POS 20UL
#define USB_DWC2_GHWCFG2_MULTIPROCINTRPT BIT(USB_DWC2_GHWCFG2_MULTIPROCINTRPT_POS)
#define USB_DWC2_GHWCFG2_DYNFIFOSIZING_POS 19UL
#define USB_DWC2_GHWCFG2_DYNFIFOSIZING BIT(USB_DWC2_GHWCFG2_DYNFIFOSIZING_POS)
#define USB_DWC2_GHWCFG2_PERIOSUPPORT_POS 18UL
#define USB_DWC2_GHWCFG2_PERIOSUPPORT BIT(USB_DWC2_GHWCFG2_PERIOSUPPORT_POS)
#define USB_DWC2_GHWCFG2_NUMHSTCHNL_POS 14UL
#define USB_DWC2_GHWCFG2_NUMHSTCHNL_MASK (0xFUL << USB_DWC2_GHWCFG2_NUMHSTCHNL_POS)
#define USB_DWC2_GHWCFG2_NUMDEVEPS_POS 10UL
#define USB_DWC2_GHWCFG2_NUMDEVEPS_MASK (0xFUL << USB_DWC2_GHWCFG2_NUMDEVEPS_POS)
#define USB_DWC2_GHWCFG2_FSPHYTYPE_POS 8UL
@ -366,6 +385,8 @@ USB_DWC2_GET_FIELD_AND_IDX_DEFINE(ghwcfg1_epdir, GHWCFG1_EPDIR)
#define USB_DWC2_GHWCFG2_HSPHYTYPE_ULPI 2
#define USB_DWC2_GHWCFG2_HSPHYTYPE_UTMIPLUS 1
#define USB_DWC2_GHWCFG2_HSPHYTYPE_NO_HS 0
#define USB_DWC2_GHWCFG2_SINGPNT_POS 5UL
#define USB_DWC2_GHWCFG2_SINGPNT BIT(USB_DWC2_GHWCFG2_SINGPNT_POS)
#define USB_DWC2_GHWCFG2_OTGARCH_POS 3UL
#define USB_DWC2_GHWCFG2_OTGARCH_MASK (0x3UL << USB_DWC2_GHWCFG2_OTGARCH_POS)
#define USB_DWC2_GHWCFG2_OTGARCH_INTERNALDMA 2
@ -381,6 +402,10 @@ USB_DWC2_GET_FIELD_AND_IDX_DEFINE(ghwcfg1_epdir, GHWCFG1_EPDIR)
#define USB_DWC2_GHWCFG2_OTGMODE_SRPOTG 1
#define USB_DWC2_GHWCFG2_OTGMODE_HNPSRP 0
USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_tknqdepth, GHWCFG2_TKNQDEPTH)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_ptxqdepth, GHWCFG2_PTXQDEPTH)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_nptxqdepth, GHWCFG2_NPTXQDEPTH)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_numhstchnl, GHWCFG2_NUMHSTCHNL)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_numdeveps, GHWCFG2_NUMDEVEPS)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_fsphytype, GHWCFG2_FSPHYTYPE)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_hsphytype, GHWCFG2_HSPHYTYPE)
@ -393,10 +418,20 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_otgmode, GHWCFG2_OTGMODE)
#define USB_DWC2_GHWCFG3_DFIFODEPTH_MASK (0xFFFFUL << USB_DWC2_GHWCFG3_DFIFODEPTH_POS)
#define USB_DWC2_GHWCFG3_LPMMODE_POS 15UL
#define USB_DWC2_GHWCFG3_LPMMODE BIT(USB_DWC2_GHWCFG3_LPMMODE_POS)
#define USB_DWC2_GHWCFG3_BCSUPPORT_POS 14UL
#define USB_DWC2_GHWCFG3_BCSUPPORT BIT(USB_DWC2_GHWCFG3_BCSUPPORT_POS)
#define USB_DWC2_GHWCFG3_HSICMODE_POS 13UL
#define USB_DWC2_GHWCFG3_HSICMODE BIT(USB_DWC2_GHWCFG3_HSICMODE_POS)
#define USB_DWC2_GHWCFG3_ADPSUPPORT_POS 12UL
#define USB_DWC2_GHWCFG3_ADPSUPPORT BIT(USB_DWC2_GHWCFG3_ADPSUPPORT_POS)
#define USB_DWC2_GHWCFG3_RSTTYPE_POS 11UL
#define USB_DWC2_GHWCFG3_RSTTYPE BIT(USB_DWC2_GHWCFG3_RSTTYPE_POS)
#define USB_DWC2_GHWCFG3_OPTFEATURE_POS 10UL
#define USB_DWC2_GHWCFG3_OPTFEATURE BIT(USB_DWC2_GHWCFG3_OPTFEATURE_POS)
#define USB_DWC2_GHWCFG3_VNDCTLSUPT_POS 9UL
#define USB_DWC2_GHWCFG3_VNDCTLSUPT BIT(USB_DWC2_GHWCFG3_VNDCTLSUPT_POS)
#define USB_DWC2_GHWCFG3_I2CINTSEL_POS 8UL
#define USB_DWC2_GHWCFG3_I2CINTSEL BIT(USB_DWC2_GHWCFG3_I2CINTSEL)
#define USB_DWC2_GHWCFG3_OTGEN_POS 7UL
#define USB_DWC2_GHWCFG3_OTGEN BIT(USB_DWC2_GHWCFG3_OTGEN_POS)
#define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_POS 4UL