Move control endpoint enable/disable calls to udc_enable()/udc_disable().
It does not change much during USB device support initialization, but
it seems to resolve an issue when starting from RAM, though the real
cause is unknown.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Prevent disabling OTG HS and USBPHY clocks
during sleep on STM32U5 series
Disabling these clocks during sleep mode
was causing USB device initialization issues
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Prevent disabling OTG HS and USBPHY clocks
during sleep on STM32U5 series
Disabling these clocks during sleep mode
was causing USB device initialization issues
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
It was observed that device ceases to work in Buffer DMA mode after GET
DEVICE QUALIFIER request is STALLed (when USB stack is limited to
Full-Speed only operation). The issue is due to missing dout feed.
Clear pending dout feed flag after bus reset (enumeration done) and
after stalled control read transfer to allow dout to be feed when
necessary.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Turn MCX series into families.
Reasoning:
1. The MCX SOCs are quite different from each other and having them all
under one family in the HWMv2 hierarchy is fruitless because there
are so many differences that it is confusing to try to introduce
family-level code and configs since they would each only apply to a
subset of the series. There is almost nothing that can be shared
between all of them. Which is why there are comments in the MCX
family files saying not to put anything in them. This is a technical
waste.
2. Therefore, turning all of them into families is almost 0 effort and
makes sense. It will allow these different types of MCX to be
further subdivided into series in the future as the MCX portfolio
expands and such division will be necessary as new SOCs within each
letter family are released.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
USB_OTG_HS_EMB_PHY macro is always defined, so
`defined(USB_OTG_HS_EMB_PHY)` always results in true. This means that
driver always selected `USB_OTG_SPEED_HIGH_IN_FULL` and never
`USB_OTG_SPEED_HIGH`.
Fix that by checking value of defined macro.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Adhere to Programming Guide with regards to when the DIEPCTL0.CNAK is
set. This allows the driver to survive abusive control transfers with
extremely short host timeouts.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
When the endpoint is re-enabled, check if the current FIFO settings can
be reused. Further work is needed to improve FIFO memory handling for
more advanced interface configurations.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `drivers` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The previous setup packet reference will simply be overwritten when the
host omits data (OUT) stage. If a new setup packet arrives before the
previous data stage is complete, free the last setup packet buffer.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Do not synchronously wait for endpoint interrupt bits when disarming
endpoints. Introduce ep_disabled k_event that makes it possible for
application to wait for the action to take effect which is necessary
when handling SetFeature(ENDPOINT_HALT) or SetInterface() requests.
This change improves incomplete iso IN and OUT handling performance,
especially when there are multiple isochronous endpoints that need
servicing.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
At High-Speed there is at most 25 us handling window for incomplete iso
IN/OUT and therefore determining which endpoints are isochronous is too
wasteful. Add lookup variable holding which isochronous endpoints are
enabled and limit the search to only enabled endpoints. For applications
with just one OUT and one IN isochronous endpoint this is optimal.
The lookup variable is updated only when mutex is held. Interrupt
handler accesses the variable read-only and in general there is no
problem is incomplete iso handling interrupt hits when the lookup
variable is updated, because:
* when endpoint is just activated, it cannot be source of incomplete
iso interrupt because the endpoint is not armed yet
* when endpoint is just deactivated, it was first disabled
If there is more than one isochronous endpoint same direction then just
relying on endpoint enabled is not necessarily optimal. However, in
order to be able to limit the search to only armed endpoints, the lookup
variable would have to be updated on every transfer preparation and
completion which would require more time-expensive synchronization.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Replace irq_lock() with spin lock which is proper synchronization
primitive that should be used. Because non-SMP implementations are
allowed to optimize spin lock to just locking interrupts the resulting
code is the same on all currently supported DWC2 targets.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Constify vendor quirks structure to not keep it in RAM. Use constified
vendor quirks structure directly if there is only one snps,dwc2 instance
to allow compiler inlining quirk implementation.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
implements option to enable double endpoint buffer to improve throughtput
for non-control endpoints.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
Otherwise the next attach could have the ISR invoked
before init has completely initialized all the required
data structures to handle the ISR properly.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Add helper to handle SOF interrupts/events and new Kconfig option to
disable SOF interrupt.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
New control transfer is started prematurely from device perspective when
host timeout occurs. Any data transfer from previous control transfer
have to be cancelled prior to handling SETUP data. Unconditionally
disable control IN endpoint to prevent race for enqueued buffer between
udc_buf_get_all() called in dwc2_handle_evt_setup() and udc_buf_peek()
called in dwc2_handle_in_xfercompl().
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Device can be considered enabled only after the Soft Disconnect bit is
cleared. Move the post enable quirk past the SftDiscon bit clear.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The USB CDC driver is unable to process any bulk IN transfers
after receiving spurious 'Clear Feature - Endpoint Halt' request
from host due to perpetual locked state caused by previously
scheduled transfer, that will never be finished, as the endpoint's state
is set to NAK. Fix by ignoring spurious request.
Signed-off-by: Piotr Ciura <piotr.ciura@hidglobal.com>
Because the same IP supports both device and host, so use
DYNAMIC_INTERRUPTS for KHCI and EHCI if both device and host
are enabled.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
- Reset specific configuration bits in
USB1_HS_PHYC->USBPHYC_CR before setting new values.
- Set the Frequency Selection (FSEL) bits to operate
the USB PHY Control Register at 24 MHz for proper communication.
- Enable the OTGPHY1 peripheral clock using LL_AHB5_GRP1_EnableClock.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
SEGGER Ozone J-Trace Code Profile identified iterations over daint value
as hot path. The iterations show at the very top of code profile because
full iteration happens whenever there is any activity on endpoint.
Optimize daint handling loops so only set bits are iterated over. While
this optimization depends on find_lsb_set() efficiency, it seems to be
worth it solely on the basis that quite often only few bits are set.
After a bit deeper analysis, I was suprised that on ARM Cortex-M33 the
find_lsb_set() approach is faster than naive iteration even if all bits
are set (which is extreme case because USB applications are unlikely to
use all 16 IN and 16 OUT endpoints simultaneously). This is due to fact
that there is only one conditional jump CBNZ and find_lsb_set() - 1
translates to RBIT + CLZ and then clearing the bit uses LSL.W + BIC.W.
Whereas the naive itation uses ADDS + CMP + BNE for the loop handling
and also has LSR.W + LSLS + BPL (+ ADD.W instruction on each iteration
to add 16 for OUT endpoints) for the continue check. Therefore the
optimized code on ARM Cortex-M33 is never worse than naive iteration.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
DWC2 core sets DIEPCTL0 SNAK when SETUP packet is received. The CNAK bit
results in device sending NAK in response to IN token sent to EP0, but
it does not modify the TxFIFO in any way. The stale data in TxFIFO can
then lead to "FIFO space is too low" error. Solve the issue by disabling
and flushing IN endpoint 0 if previous control transfer did not finish.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
This supports nuvoton numaker m55m1x series soc. Besides, it also
has relevant modifications, including:
1. Fix failure to enable HICR48M, which is to clock usbd and phy
2. Support HWINFO for USB device serial number
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
The UDC driver for this beautiful USB controller is mostly rewritten
from scratch. USB Pad Calibration and clock handling are copied from the
usb_dc_sam0 driver.
The driver uses multipacket transfers for all endpoints except the OUT
control endpoint. The OUT control endpoint has a buffer that is always
mapped to the endpoint buffer register so that it always has a valid
buffer. The driver provides up to 7 IN and 7 OUT endpoints that support
any type of transfer. Double buffering is not used, for the possible
case of isochronous transfers some changes would be required in the
future.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
- Removing the unused declaration of 'ret'
in the usb_dc_stm32_init function for STM32N6.
- Ensuring the 'ret' variable is used correctly
in the pinctrl_apply_state function call.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
- Unified the handling of USB OTG HS and USB OTG FS
by removing redundant preprocessor conditionals.
- Introduced a new macro `UDC_STM32_BASE_ADDRESS`
to dynamically set the USB base address.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Enable clock and power for the OTG HS peripheral
of the STM32N6x serie
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
At high throughput, the controller sometimes fails to start a new
transaction. Clearing the corresponding endpoint bit in the BUFF_STATUS
completion register before initiating a new transaction solves this
problem.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Do not check if the tailroom is greater than or equal to MPS because the
controller does not write directly to the buffer and therefore cannot
write outside the buffer.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
For the IN endpoint, we only need to set/reset the STALL bit in the
endpoint control register.
To set halt on the OUT endpoint, the AVAILABLE bit must also be set,
which is similar to starting a new transfer, but first any transfer in
progress must be canceled.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Support VBUS state change detection and enable/disable DP pull-up
according to VBUS state when pinctrl property is provided.
It brings the similar functionality introduced in commit 4c0317fa47
("drivers: usb_dc_rpi_pico: Implemented vbus detection handling")
for the legacy device controller driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Using k_events eliminates the drawback of the queue potentially dropping
messages and provides a reliable event notification mechanism. It is
similar to commit c2f2d8ce5d
("drivers: usb: udc_dwc2: Replace queue with events")
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
