Use the endpoint maximum packet size when deciding whether an IN
transfer ended with a short packet. Comparing the received byte count
against the controller maximum incorrectly completes transfers on
endpoints with smaller packets.
This allows descriptor transfers from low-speed devices, whose endpoint
zero maximum packet size is eight bytes, to span multiple packets.
Signed-off-by: Benjamin Jurewicz <bjurewicz@internships.antmicro.com>
Add DWC2 vendor quirk for xmc4xxx SoC family.
The driver does not seem to support DMA mode on the older core versions.
The symptoms are: stalled setup transfers, no responses to IN tokens on
control or other IN endpoints.
Disable internal DMA mode by default for XMC4XXX SoC series.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Generic snps,dwc2 instances do not have the vendor quirk data/config
objects emitted by the vendor-specific quirk headers. The driver already
allowed the quirk table pointer to be NULL, but still initialized
quirk_data and quirk_config unconditionally. This causes generic-only
instances to fail to build because the corresponding vendor symbols do
not exist.
Use the same vendor-quirk condition for the table, data, and config
pointers so generic instances get NULL quirk pointers.
Fixes: 89a75416b7 ("drivers: usb: uhc_dwc2: add initial support")
Signed-off-by: Duc Viet Le <levietduc0712@gmail.com>
Query the frequency of the OTG_HS PHY and compute the appropriate CLKSEL
value at runtime if the `clock-reference` property is not specified.
This removes the user burden of providing the same value twice in DTS.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Instead of using a hardcoded FSEL for 24 MHz input, query the frequency
of the USBPHYC clock and determine the correct value automatically at
runtime.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Using k_events eliminates the drawback of the queue potentially dropping
messages and provides a reliable event notification mechanism.
With the commit c3109b9ebe
("usb: device_next: cdc_acm: rx throughput improvements"),
the CDC implementation queues as many buffers as are available.
The default UDC_KINETIS_EVENT_COUNT was set to 4, and it could already
be observed that the events are dropped. Though the number of
UDC_KINETIS_EVENT_COUNT could be increased, using k_events is the right
fix.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Align the driver design with most of the drivers in the tree and move
driver event handling from the UDC workqueue to the driver's own thread.
Driver thread handles the events under UDC internal lock and makes it
mutually exclusive with API calls. Add k_sched_lock() UDC internal lock
to avoid unnecessary context switch to the driver thread triggered by
e.g. interrupt event, while the internal lock is still held.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
STM32Cube OTG HAL aborts and disables an ISO IN endpoint on IISOIXFR
and invokes HAL_PCD_ISOINIncompleteCallback instead of DataInStage.
The UDC driver ignored that, so the endpoint stayed busy and UAC2
capture went silent after the first missed frame. Drop the missed
packet through the normal IN completion path so the next buffer can
be armed, matching ISO OUT recovery.
Assisted-by: Cursor:grok-4.6
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
HAL_PCD_ISOOUTIncompleteCallback() and HAL_PCD_ISOINIncompleteCallback()
sat below HAL_PCD_DataOutStageCallback(), but the file only keeps the
Setup/DataIn/DataOut callbacks next to their worker-thread handlers.
Move them up with the other HAL callbacks. No functional change.
Assisted-by: Claude:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The SAM0 USB device controller never enabled the SOF interrupt, so
UAC2 SOF callbacks never ran and audio capture stayed silent. Round
PCKSIZE.SIZE up to the next supported hardware value so isochronous
MPS such as 192 bytes (48 kHz 16-bit stereo) can be programmed.
Assisted-by: Cursor:grok-4.6
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
With the commit c3109b9ebe
("usb: device_next: cdc_acm: rx throughput improvements"),
the CDC implementation queues as many buffers as are available. This may
trigger an error log, "<err> udc_rpi_pico: Endpoint 0x01 busy".
There is nothing wrong with the driver, it is just that another transfer
is queued while an endpoint is busy.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Two-line copyright notices were wrapped in the SPDX "<text>...</text>"
construct, which is only valid in an SPDX document, not a file header.
The REUSE tool then folds the literal "<text>" into the holder name
and drops the second line from the SBOM.
Remove the markers and tag the continuation line. Holder, year and
e-mail are left unchanged; only the syntax is fixed.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Replace direct NVIC_SetPendingIRQ()/NVIC_ClearPendingIRQ()/
NVIC_EnableIRQ() calls with the portable k_irq_set_pending()/
k_irq_clear_pending()/irq_enable() equivalents. The Smartbond DA1469x
is a plain-NVIC Cortex-M33, so the pending-state capabilities are
always available where this code builds.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The endpoint buffers live in the USB DPRAM, which is in the peripheral
(Device) memory region. On Armv8-M (Cortex-M33) Device memory must be
accessed naturally aligned regardless of CCR.UNALIGN_TRP, so an unaligned
half-word or word access raises a UsageFault.
The payload was copied with plain memcpy()/net_buf_add_mem(). picolibc's
Armv7-M memcpy finishes a 3-byte tail (e.g. the 31-byte USB MSC Command
Block Wrapper) with a byte copy followed by a half-word copy at an odd
address, which faults against the DPRAM. RP2040 (Cortex-M0+) is unaffected
because its libc memcpy is byte-wise.
Copy the word-multiple part with memcpy() and the remainder byte by byte.
Fixes#111789
Assisted-by: Claude:claude-opus-5
Signed-off-by: Andreas Petter <Andreas.Petter@mcnetic.de>
The STM32 OTG (dwc2) core raises the incomplete-isochronous interrupt and
disables an isochronous endpoint when a transfer misses its (micro)frame,
for example when the endpoint ended up armed for the wrong even/odd frame.
The HAL handles this by disabling the endpoint and then invoking
HAL_PCD_ISOOUTIncompleteCallback(), but udc_stm32 never implemented it, so
the endpoint stayed disabled and was never re-armed.
As a result isochronous OUT reception stalls permanently after the first
missed frame: a UAC2 host-to-device (playback) stream delivers a few
zero-length packets and then goes idle, with the application seeing
data_recv with size 0. Isochronous IN (e.g. a UAC2 microphone) degrades
gracefully, so only the OUT direction was visibly broken.
Implement HAL_PCD_ISOOUTIncompleteCallback() to re-arm the pending
receive via HAL_PCD_EP_Receive(), which re-selects the correct even/odd
frame parity at arm time and resynchronises the endpoint. Recovering
isochronous IN requires going through the normal data-in completion path
and is left as a follow-up.
Verified on an STM32U575 (OTG-FS) UAC2 composite device: host playback now
reaches the peripheral continuously instead of stalling after a few frames.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Peter Buchegger <peter.buchegger7@gmail.com>
The esp32p4 fsls phy pads are shared with usb-serial-jtag
through an lp_sys mux that defaults to the usj. Hand the pads
to the otg-fs controller when the phy is enabled and return
them to usb-serial-jtag in the disable quirk. The usj console
and flashing keep working until the device stack is enabled
and are restored at runtime once the stack is disabled,
without a chip reset.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Remove CONFIG_NOCACHE_MEMORY conditional code and associated nocache
memory allocation/deallocation logic from uhc_mcux_ehci driver.
The setup packet and transfer buffers are now handled by the common
UHC layer with proper cache alignment, making driver-specific nocache
memory management unnecessary.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Change setup_pkt to be usb requested address and size aligned,
This allows the setup packet buffer to be cache line size aligned.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Use the uhc_dwc2_get_base() in port_suspend()
and port_resume() as the base member is available
via helper, that calls DEVICE_MMIO_NAMED_GET as a
follow-up for 528a0627ed.
Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
dwc2_core_init_host_gusbcfg() reads GUSBCFG register value, modifies the
register to force host mode but does not read the actual register value
back. Using an outdated value later the dwc2_core_init_host_gusbcfg()
reverts to device mode. The bug is only observable on boards with
ID-pin not grounded.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
That is the only driver in the tree that uses odd flags from the
bitfield in struct udc_ep_stat. udc_ep_stat may have RMW bugs due to
bitfields modified from different contexts. The use of odd bitfield is
safe in this driver, as all writes are in the ISR handler.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add support for STM32H5E/F line SoCs: in particular, the power
initialization sequence for OTG_HS usage was incomplete.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Implement suspend, resume and remote wakeup. Make sof_enable callback a
no-op because controller automatically handles SOF generation when the
port is not suspended.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Some Renesas RA USBFS variants only have 5 pipes with a different
pipe layout compared to the standard variant:
- Pipe 0: control transfer
- Pipes 4-5: bulk transfer only
- Pipes 6-7: interrupt transfer only
- No isochronous support
Previously, all non-control endpoints were unconditionally advertised
as supporting bulk, interrupt, and isochronous transfers, which is
incorrect for this variant
Therefore shim-code udc_renesas_ra.c needed changes to properly configure
the pipe-configuration for this 5-pipe usbfs variant.
Signed-off-by: Victor Hogeweij <hogeweyv@gmail.com>
The MCUX EHCI and IP3511 hs controllers can detect VBUS state before
udc_enable (which pulls up DP) is called when the underlying MCUX USB
device hal drivers are built with USB_DEVICE_CONFIG_DETACH_ENABLE.
Set the can_detect_vbus capability accordingly so the USB device stack
can rely on hardware VBUS detection when available.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
The "st,stm32-usbphyc" compatible was used for three different hardware
programming models, which goes against the Devicetree Specification.
This was masked though special checks in CMake which is hacky at best.
Split the compatible in three compatibles (2 new + 1 reused):
- "st,stm32-usbphyc" where the PHY clock frequency is configured
through USBPHYC registers in the RCC MMIO interface (STM32H7R/S)
- "st,stm32f7-usbphyc" where the PHY clock frequency is configured
through a distinct MMIO interface with five options available:
12, 12.5, 16, 24 and 25 MHz
- "st,stm32n6-usbphyc" where the PHY clock frequency is configured
through a distinct MMIO interface with three options available:
19.2, 20 and 24 MHz
Update SoC DTSI and drivers (Kconfig, CMakeLists and source) to work
with the new organization brought by these bindings.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ ./scripts/check_quoted_includes.py -w drivers/usb/
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This macro eliminates manual size/alignment management and prevents
namespace collisions by moving internal queues to file-private scope.
Signed-off-by: Cesar Vandevelde <cesar.vandevelde@gmail.com>
Enable the full-speed USB device controller on STM32L1:
- Assert PLL VCO = 96 MHz at build time (USB clock = VCO / 2).
- Skip the runtime 48 MHz clock check; the clock is deterministic.
- Drive the DP pull-up via SYSCFG_PMC USB_PU (no disconnect GPIO).
- Add the usb controller node and a nop USB PHY in devicetree.
Signed-off-by: Florian Moesch <florian.moesch@draeger.com>
The Kconfig options related to USB common code should be gated by the
STM32_USB_COMMON option. Otherwise, they can appear in Kconfig of builds
where USB is not enabled at all (notably, the options related to logging
configuration were always leaked)
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a new pseudo-driver for USBPHYC instances whose input frequency
selection is configured at RCC level in a `CCIPR` register, as is
the case on STM32H7R/S series for example.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
For non-control out endpoints, do not submit the out event to upper
stack until the transfer buffer is completely filled.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Re-initializing the suspend work when it's busy may cause kernel
panic. This change moves the suspend work initialization to the pre-init
function to ensure it is initialized only once.
Tested with: sudo dfu-util --detach
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Enable the GPIO subsystem when the driver is enabled if disconnect-gpios
are provided on a node with compatible `st,stm32-usb` or if an ULPI PHY
provides reset-gpios.
The second case should be handled at a generic level, but ULPI PHYs have
always been managed as part of the STM32 driver for historical reasons.
Since no SoC family other than STM32 seems to use ULPI PHYs, this code
remains vendor-specific for now.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use Zephyr's standard MMIO abstraction API by introducing
DEVICE_MMIO_NAMED_RAM/ROM(core) in the driver's data and
config structs, mapping the region at initialization time
with DEVICE_MMIO_NAMED_MAP, and routing all register accesses
through a uhc_dwc2_get_base() helper that calls DEVICE_MMIO_NAMED_GET.
These changes allows the driver to be useful on MMU-based
platforms like Broadcom BCM2711 SoC.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Use the `%zu` format specifier when printing `size_t` values instead of
`%u`. On 64-bit platforms, using an incorrect format specifier is
causing compiler warnings due to type mismatches.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Rename the existing full-speed uhc quirk to the speed specific
espressif,esp32-usb-otg-fs compatible, that was introduced
in #111508.
Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
Replace IS_EQ() + DT_ENUM_IDX() with the simpler and more explicit
DT_ENUM_HAS_VALUE() macro.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The COND_CASE_1() allows writing chained/nested COND_CODE_1() checks in
a simpler way. Replace such patterns in the STM32 drivers with this new
utility macro.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Previously Max3421e driver locked and unlocked `uhc_data` mutex by using
`k_mutex_lock()` and `k_mutex_unlock()` instead the already existing
uhc helpers: `uhc_lock_internal()` and `uhc_unlock_internal()`.
Signed-off-by: Benjamin Jurewicz <bjurewicz@internships.antmicro.com>
Add the ESP32-P4 USB-OTG high-speed controller using the
espressif,esp32-usb-otg-hs binding and the internal UTMI PHY. The
high-speed PHY uses dedicated pins, so no pad configuration is
needed. Enable the controller on the function ev board.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Introduce a shared Espressif USB-OTG binding scheme and rename the
existing full-speed quirk to the speed specific
espressif,esp32-usb-otg-fs compatible. The internal PHY D+/D- pad
numbers now come from the phy-dp-pin and phy-dm-pin device tree
properties, so migrate the esp32s3 node accordingly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add vendor quirks for nRF54LM20 PHY configuration for DWC2 in host mode.
Given the PHY is powered from USB, the PHY needs to be configured and
powered on before registers can be accessed or the SoC freezes on any
register access.
Signed-off-by: Josuah Demangeon <josuah.demangeon@nordicsemi.no>
