Fix error writing to the CR register on the first call to SPI configure on
NXP MKE1xF. On the first call, the module clock is not enabled and writing
to the CR register will fail.
Fixes: #66036
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Simplify and clarify spi_stm32_shift_m by splitting it in
3 smaller functions with clear names.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
In H7, TXP indicates when its FIFO has room for, at least, one
packet. Thus, rename ll_func_tx_is_empty as ll_func_tx_is_not_full,
to be consistent in all platforms.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Avoind calling startMasterTransfer multiple times in a
transaction by moving it to the transceive() function.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
While enabling workaround for PAN 58 the PPI driver is used.
This requires the nrfx PPI driver to be enabled thus CONFIG_NRFX_PPI
Kconfig symbol needs to be set.
Jira: NRFX-1616
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
This check has to be done independent of whether RAM is used for buffers
or not and depends on device maximum length property.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Instead of assuming only RAM is accessible by EasyDMA, use the generic
DMA accessible function.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Some targets may not have `NRF_SPIM_HAS_32_MHZ_FREQ` or
`NRF_SPIM_HAS_16_MHZ_FREQ` symbols but have `NRF_SPIM_HAS_PRESCALER`
symbol defined. The symbol informs that target supports 32 MHz and
16 MHz frequencies for SPIM instances.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
The CLOCK HAL header is only needed for nRF5340 SoC. It's used when
user wants to configure SPIM instance to 32 Mbps. The HAL checks
if is running at 128 MHz as only then 32 Mbps is supported.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
In the case where a transaction is spilt due to the rx buff len
being longer than the tx or the transaction buffer exceeding the
size of the requested buffer with non gpio CS, the chip select
would be de-asserted/asserted in the middle of the transaction.
Fixes: #57577
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
For some STM32 MCUs the busy flag of SPI is unreliable. This is a known
issue of the device and described in the device errata.
As a fix implement a configurable timeout which ensures that a call
to spi_transceive will eventually return.
Fixes#64927
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Set Spi StateIndex equal to index of DT Spi node.
Because number of State array is set base on
number of DT Spi node used. If StateIndex is set
equal to Spi instance, StateIndex can be over array.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Fixes an unhandled interrupt runtime crash if CONFIG_SPI_XMC4XXX_DMA=y and
CONFIG_SPI_XMC4XXX_INTERRUPT=n.
The unhandled interrupt error is triggered because irq_enable() was called
without calling IRQ_CONNECT() when CONFIG_SPI_XMC4XXX_INTERRUPT=n.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In the interrupt driven spi, spi_context_update_tx() is called once
from the calling thread and then once in spi_xmc4xxx_isr() after each
new byte is received. This actually means that there is one extra call to
spi_context_update_tx(). This is fine if spi_context_update_tx() complete
it's call in the calling thread before the interrupt fires, however, this
cannot be guaranteed especially if the calling thread is pre-emptive and
has a low priority.
Fix this by calling spi_context_update_tx() in the calling thread before
transmitting the first byte.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Move the syscall_handler.h header, used internally only to a dedicated
internal folder that should not be used outside of Zephyr.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a new SPI shim driver for Intel SoCs. Builds upon the SEDI bare
metal SPI driver in the hal-intel module.
Co-Authored-By: Kong Li <li.kong@intel.com>
Signed-off-by: Ye Weize <weize.ye@intel.com>
Updated the Async API allowing the code path
for DMA while Async is enabled. Added common
DMA function that sets up both tx and rx dma
channels.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
The instruction length can only be 0~5.
Use am_hal_iom_blocking_transfer and specify clearly the TX/RX direction.
Hold CS to continue to RX expected response after instruction transmission.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The commit fixes the SPI mode improper configuration.
Otherwise the MODE_3 and MODE_0 cases would never be entered as expected.
Signed-off-by: Aaron Ye <aye@ambiq.com>
SPI API allows `spi_buf_set` structures with no buffers linked to them
(with `.buffers = NULL`). Correct the spi_nrfx_spis driver so that it
is able to deal with such structures.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
NOCACHE_MEMORY depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT, so
don't try to select the symbol if not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Currently, the driver imply understand that all instances
will use dma when CONFIG_SPI_MCUX_LPSPI_DMA is set. There
might be an instance doesn't need DMA, so instead of enforce
spi_transceive API to use DMA, add more flexible to enable
DMA only when required
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Modify STM32H7 SPI driver so that it updates the rx/tx
pointers correctly (depending on the frame size) when DMA
is enabled. Also, make the dummy rx/tx buffer cache-coherent.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
The way of setting a nocache region in devicetree has changed.
Adapt the H7 SPI driver to this new circumstance.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Drivers for nRF SoCs using pinctrl did not select PINCTRL. This means
boards are forced to enable PINCTRL.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Drivers should only log extra information during initialization if
debug logging is enabled. Otherwise it always clutters the console
when not required.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Zephyr version 3.4 changed the SPI context structure and macros
which broke the logic in the MEC172x SPI driver configuration API.
This was not detected by CI due to no tests for this driver are in
the tree. The driver now behaves like most other SPI drivers requiring
a different configuration structure pointer to be passed if any item
in the configuration changes.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Initial version of Infineon CAT1 SPI Driver supporting synchronous
and asynchronous data transfer API
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
When doing a TX-only SPI operation, the RX not empty flag will never get
set, thus this will just hang forever.
Found/tested on STM32L462 trying to drive some WS2812 RGB LEDs.
Signed-off-by: David Lamparter <equinox@diac24.net>
Add fundamental feature support for RP2040 PIO SPI peripherals.
This commit implements synchronous transfer with 8-bit MSB
format. Using PIO allows any GPIO pins to be assigned the roles
of CS, CLK, MOSI, and MISO.
Optional features not implemented yet:
- Interrupt based transfer
- DMA transfer
- Slave mode
- Varying word size
- 3-wire SPI support
- LSB-first
Updated in response to review comments.
Further updates from second round of review.
Rename spi_pico_pio.c source to match zephyr/MAINTAINERS.yml
Remove unnecessary initialization code.
Resolve merge conflicts
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Check the TXC flag instead of EOT for the case of endless
transactions (TSIZE = 0), which in this case is always as
the stm32 SPI driver doesn't set TSIZE.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
