This adds the missing fifo config from the dts which was missed in
the initial revision. This also adds the spi rtio fallback api.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Replace semaphores with proper atomic flags when used without
multithreading enabled.
Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
The nrxf_spim driver currently resumes itself for the duration of
a transfer, however, in case SPI_LOCK_ON is used, the driver needs
to keep itself resumed until spi_release() is called. Currently,
this results in unbalanced suspend as the bus puts itself both
after transaction is done, and when spi_release() is called.
This patch makes the driver check if SPI_LOCK_ON is set once
transaction is complete, if yes, selv get one more time to
account for the two puts which will follow.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This dependency was always there but not explicitly defined.
By adding the explicit dependency it becomes more obvious
what is wrong when SPI is enabled but GPIO disabled.
This was found when building `samples/bluetooth/peripheral`
for `nrf54l15dk/nrf54l15/cpuapp` with `CONFIG_GPIO=n`.
Before we got:
- A linker error in `spi_nrfx_common.c` failing
to reference some nrfx_gpiote APIs.
- A linker error in `spi_nrfx_spim.c` failing to reference
the GPIO dts entry.
Now we will get a warning of that GPIO is not enabled
With this it becomes more obvious that SPI driver is enabled by
default because of the external flash mounted on the DK.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
SPI driver for Microchip MEC5 HAL based QSPI controller. QSPI
hardware supports full duplex, dual, and quad operation. MEC5
QSPI controller also includes three local DMA channels per
direction to off load firmware. The driver API supports full
or half-duplex. Due to QSPI hardware not supporting one wire
half-duplex, this driver supports full-duplex only. QSPI hardware
design requires it to control chip select and current hardware
supports up to two chip selects. Zephyr's SPI DT macros store the
child SPI device's reg properity as the "slave" member of the SPI
configuration structure. The driver uses the "slave" value as the
chip select. Additional timing settings specific to SPI flash devices
are in a new SPI device YAM file: "microchip,mec5-qspi-device.yaml"
which includes the standard "spi-device.yaml". If the new YAML is not
used, the QSPI controller will use default timing values for chip
select and I/O line taps.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
There was a race condition where `lpspi_end_xfer` can be called multiple
times per transfer. There was the case where a TX interrupt gets
triggered without the RX interrupt being set, and TX finishes writing
its last byte. Then, `spi_context_rx_len_left() == 0` is true and
`lpspi_end_xfer` happens, but the RX interrupt is still active. Then,
when the RX interrupt happens, `lpspi_end_xfer` will get called again.
To fix that, the architecture was adjusted to only call `lpspi_end_xfer`
once no interrupts are active any more, and the disabling of the
interrupts gets used to signal the end of the TX and RX part.
Minor adjustments were necessary to use the interrupt enable signals for
this purpose; the TX irq handler had its internal order reversed,
otherwise it wasn't guaranteed that the physical transfer is finished
when we disable the interrupt.
Also, the code where the RX interrupt gets disabled had to be moved out
of the RX irq handler, because the RX interrupt also needs to be
disabled if RX is finished but no RX interrupt is currently active.
Signed-off-by: Martin Stumpf <finomnis@gmail.com>
In case the SPI transaction has SPI_HOLD_ON_CS set, we need to keep
SPI resumed until spi_release() is called. This is required as we
now need to keep the CS GPIO port resumed until transaction is
complete.
Suspending CS GPIO is not allowed from ISR in some cases (H20 fast
GPIO instance) so we have to defer CS GPIO suspend to some thread
context (put_async or spi_release()).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Implement calling spi_context_cs_get_all() and
spi_context_cs_put_all() in line with pm resume/suspend.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Introduce spi_context_cs_get() and spi_context_cs_put() which shall
be used from drivers to get/put the GPIO port the CS GPIO belongs to
before and after a transaction, in line with the SPI drivers pm
action hook being called.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Changed to define ambiq spi/i2c dma mode as a binding property
instead of kconfig macros, making it more flexible for different
spi/i2c instances.
Signed-off-by: Hao Luo <hluo@ambiq.com>
1. rework IOM cmdq buffer instantiation
2. rework spi and i2c cache handling as it is incorrect.
3. buffers need to be aligned with DCACHE on
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The TXFTLR register has 2 major fields which are TFT for triggering
interrupt threshold and TXFTLR for starting transfer threshold. This is
to ensure that sufficient data is ready for starting transfer.
Signed-off-by: Younghyun Park <younghyunpark@google.com>
Support SPI_HOLD_ON_CS flag in the CPU-based driver. To do this we will
set CONTC bit to continue previous command. Technically it may not be
necessary right now, and could just not clear CONT bit...
but in the future in the lpspi driver we
will decouple the config/init of a transfer from the SDK
and therefore have more control over TCR,
and when we write the TCR, we need to take CONTC bit into account
otherwise a new command will be made. So this approach is how
it should be handled in the driver going forward in my opinion, even
if it might be possible without this bit right now, I want to introduce
it's usage now.
This commit also does a minor refactor in the ISR and adds some comments
to make the strange CS behavior and strange handling code more clear to
future readers.
Also, make the early predicted SPI xfer end code only happen for spi
versions where it is necessary, since I think that code is really the
best we can do but might have a race condition, where possible the last
word is not finished sending when we end the xfer. So limit the
potential affect to v1 lpspi where the workaround is actually required
due to stalling behavior.
Lastly, set the LPSPI into master mode at active low in init, due to
it being the most common case, we want the SPI CS lines to be
initialized at init of driver. I don't think it's worth it to make it
configurable at this time, but in the future it could be if needed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The LPSPI does support word sizes such as 6 or 7, anything as small as 2
bits. So fix the checks and the math to allow for this in the driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Optimize the TX fill algorithm to have less interrupts by filling the TX
fifo as much as possible during each interrupt handle.
Before, the algorithm was just a very simple, fill the TX fifo with as
much from only the current buffer as possible, then send it and wait for
the next interrupt. Now the algorithm is to fill the TX fifo as much as
possible, even if it means reading from multiple buffers during the
interrupt.
This has the advantage from master mode of having less interrupts. And
it is very important for slave mode because the slave mode does not
control the pacing of the transfer and so therefore should fill as much
as possible whenever possible in order not to miss a deadline.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for SPI to cc23x0 SoC. Only controller mode is implemented.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
ISR safe runtime PM can only be used for all instances except for
spis120 which requires standard runtime PM.
Added compilation guard against using CONFIG_PM_DEVICE_SYSTEM_MANAGED
with spis120.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add FOREACH macro which iterates over all SPIM instances and creates
device instances for each enabled instance.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add compile time detection if fast SPIM instances are used
and system managed device PM is enabled. This configuration is
not supported.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Since these drivers mainly do not use MCUX except for the configure
function (which will soon also be changed), change namespace prefix to
lpspi_ instead of spi_mcux_ to avoid confusion.
Also improve descriptions of kconfigs to clarify what they are for.
Not changing the kconfig names for now since they are user-facing.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove SDK types and defines from header file.
And since now the common file is the only consumer of SDK header, move
that include there.
Also rename the tristate boolean to be more clean about what it does
rather than trying to be similar to the SDK config name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
We should not release context until transfer ends. The code previously
would return from wait_for_completion and then release the context. This
is only supposed to be done in the dma callback except for the case of
error in the transceive call. For async transfer this was most likely
always happening wrong and probably broken for multi threads trying to
access the bus due to this premature release of the context.
Also we should not enable CS and leave enabled in case of error, move CS
enable to after the error check.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Stop the transfer with error if at any point there is some
execution reached where transfer is being set up for 0 length, this can
cause problems where for example eDMA set up with this nonsense 0 length
channels can get an infinite error interrupt.
And this is probably an erroneously crafted transfer request anyways.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
If there are HAL definitions available, do these two things:
Ungate the clock for the device from the zephyr driver. Eventually it
would be better to have a clocks property in the LPSPI DT node and get
the resources from there rather than the HAL.
Some platforms require the peripheral to be reset at system level, add
code to do this. Eventually it would be more ideal to have Zephyr
reset drivers for all of the NXP platforms and use DT to describe the
reset resources, but for now we can just do this to get the LPSPI
supported.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit adds ambiq iom binding file to consolidate
spi and i2c that share the same IO Master module on
Apollo MCUs
Signed-off-by: Hao Luo <hluo@ambiq.com>
Drivers update to use shared interrupt allocator for Xtensa
and RISCV devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Allow STM32 SPI driver to operate with DMA support even when
CONFIG_MEM_ATTR is disabled which happen when CONFIG_ARM_MPU is
intentionally disabled despite the CPU supports MPU.
By the way, remove some #ifdef directive on header files inclusion
that add noise in the header file inclusion section without any
benefit.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The passive level of the clock does not change instanteneously when
it's set using function XMC_SPI_CH_ConfigureShiftClockOutput().
This means that the passive level of the clock can be in the wrong
state when the chip select goes low.
Fix this by adding a small delay when the polarity changes to allow
the clock to return to the proper level.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
