Add option to use (by defining the `wake-gpios` devicetree properties)
an additional signal line between SPI master and SPI slave that allows
the latter to stay in low-power state and wake up only when a transfer
is to occur.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
and enabled proper nrfx driver instance; instead, use one option per
peripheral type and include the corresponding shim driver flavor into
compilation basing on that option (not the one that enables the nrfx
driver as it was incorrectly done so far in some cases)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add driver for OpenTitan SPI host.
Tested and verified single SPI full duplex on opentitan_earlgrey in
Verilator.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Zephyr SPI driver model for full-duplex operation assumes
data will be transmitted and received during each clock period.
The QMSPI driver for the XEC family also supported dual and
quad I/O use cases which are inherently half-duplex. To
support dual/quad the driver incorrectly processed spi buffers
as all transmit buffers first then all receive buffers. This
worked if only the SPI driver was used. It did not work with
the Zephyr flash SPI NOR driver which assumes SPI drivers
follow the SPI driver model. This commit implements a QMSPI
driver that follows the Zephyr SPI driver model resulting in
a slightly smaller driver. Dual/quad SPI transactions are
supported if the experimental SPI extended mode Zephyr
configuration flag is enabled. We also remove the QMSPI full duplex
driver added previously to support the flash SPI NOR driver.
Added board to spi loop-back test and spi_flash sample.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Provides a macro and submit API for SPI drivers to support RTIO.
A copy function enables compatibility with the existing blocking API
and very easily the existing async API as well.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add MEC172x full duplex qmspi driver version to support full
duplex transfers as expected by the Zephyr spi driver model.
On every spi clock we transmit one bit and receive one bit.
This driver will work with Zephyr SPI NOR driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Adds a new spi_transcieve_cb API which enables asynchronous
SPI transactions with callback notification.
The exist spi_transcieve_async API remains and uses the new
spi_transcieve_cb API to provide a k_poll_signal notifier.
The driver API changes to provide a callback and userdata
parameter to async transcieve. All drivers in the tree
have been updated to the change.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add fundamental feature support for PL022 SPI peripheral.
This commit implements synchronous transfer with 8bit-MSB format.
Optional functions are not currently implemented yet.
- interrupt based transfer is not implemented yet.
- DMA transfer is not implemented yet.
- Slave mode is not implemented yet.
- Currently support only 8-bit data transfer.
Hardware limitation:
- LSB-first format is not supported by hardware.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
This patch adds driver for the Microchip Polarfire SOC MSS QSPI
controller.
The interrupts of the MSS QSPI are routed through PLIC(Platform level
interrupt controller).
Tested with generic spi-nor flash driver(spi_flash) with both Fixed
flash configuration and Read flash parameters at runtime(using SFDP).
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This adds an spi master mode driver via bitbanged gpio. Only syncronous
transfers are implemented. Clock signal timing is accomplished via busy
waits, the gpios are manipulated via the standard gpio interface; these
two factors limit the frequency at which it can operate - but here
a simple and generic implementation was chosen over performance.
The driver supports the various clock polarity and phase
configurations, and can also work with word sizes which are non
multiples of 8bits, currently up to 16 bits.
A sample program is also added demonstrating basic use of the driver
with 9bit data words.
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface
to access the SPI flash. This commit adds the driver support for it.
With this commit, the application can call the flash APIs
(via spi_nor.c) to access the internal flash of NPCX EC chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
We will need this to be able to DEVICE_DT_GET() bus devices from
tests/drivers/build_all in an upcoming commit.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add an emulation controller which routes SPI traffic to an attached
emulator. Only one emulator is supported per bus at present, since
chip-selction functionality is not present.
This allows drivers for SPI peripherals to be tested on systems that
don't have that peripheral attached, with the emulator handling the SPI
traffic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add SPI driver for the Xilinx AXI Quad SPI IP. Despite the name, this IP
block supports both single, dual, and quad line widths.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit adds SPI driver and its bindings using the USART peripheral
for Silicon Labs EFM32 and EFR32 MCUs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Adds a shim layer around the mcux lpc flexcomm driver to adapt it to the
zephyr spi interface. It leverages heavily from the existing mcux dspi
shim driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC.
Based heavily on the existing mcux LPSPI driver.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
This commit adds LiteX SPI drivers and its bindings.
Signed-off-by: Daniel Craviee <dcraviee@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This was only used on Quark SoCs. It is no longer used, can no
longer be tested, and it's reliant upon the deprecated legacy PCI
subsystem. Remove it to prevent bitrot.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduces a new mcux lpspi shim driver to be used on the imxrt soc.
This shim driver leverages heavily from the mcux dspi shim driver
because the MCUXpresso SDK provides similar APIs for the lpspi and dspi
peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Normally a syscall would check the current privilege level and then
decide to go to _impl_<syscall> directly or go through a
_handler_<syscall>.
__ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will
make all the system calls from the driver files directly link
to the _impl_<syscall>. Thereby reducing the overhead of checking the
privileges.
In the previous implementation all the source files would be compiled
by zephyr_source() rule. This means that zephyr_* is a catchall CMake
library for source files that can be built purely with the include
paths, defines, and other compiler flags that all zephyr source
files uses. This states that adding one extra compiler flag for only
one complete directory would fail.
This limitation can be overcome by using zephyr_libray* APIs. This
creates a library for the required directories and it also supports
directory level properties.
Hence we use zephyr_library* to create a new library with
macro _ZEPHYR_SUPERVISOR_ for the optimization.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This adds a translation layer to make the nrfx driver for the nRF SPIS
(SPI Slave with EasyDMA) peripheral accessible via the Zephyr's API.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds a translation layer to make the nrfx driver for the nRF SPIM
(SPI Master with EasyDMA) peripheral accessible via the Zephyr's API.
The shim is provided only for nRF52840 because of a hardware anomaly
present in nRF52832. See Anomaly 58 (SPIM: An additional byte is clocked
out when RXD.MAXCNT = 1) in Errata for this chip.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds a translation layer to make the nrfx driver for the legacy
(i.e. without EasyDMA) nRF SPI peripheral accessible via the updated
Zephyr's API of the SPI driver.
Configuration files are already prepared for adding support for SPIM
(Master with EasyDMA) and SPIS (Slave with EasyDMA) peripherals.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Now that MCR20A supports the new API, legacy support from mcux dspi
driver can be safely removed.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Adds support for the new spi api to the mcux dspi shim driver. Does not
remove support for the legacy spi api since there are still consumers of
that api, particularly the mcr20a 802.15.4 driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
