drivers/spi: Switch Intel driver to new SPI API
Ditch any legacy API support altogether. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
parent
b4247fde4d
commit
65f6c96736
6 changed files with 305 additions and 343 deletions
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@ -1,10 +1,10 @@
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if(CONFIG_SPI_LEGACY_API)
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zephyr_sources_ifdef(CONFIG_SPIM_NRF52 spim_nrf52_legacy.c)
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zephyr_sources_ifdef(CONFIG_SPIS_NRF5 spis_nrf5_legacy.c)
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zephyr_sources_ifdef(CONFIG_SPI_INTEL spi_intel.c)
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zephyr_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
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else()
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zephyr_sources_ifdef(CONFIG_SPI_DW spi_dw.c)
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zephyr_sources_ifdef(CONFIG_SPI_INTEL spi_intel.c)
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zephyr_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
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zephyr_sources_ifdef(CONFIG_SPI_SAM0 spi_sam0.c)
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endif()
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@ -290,6 +290,14 @@ config SPI_5_OP_MODES
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if SPI_LEGACY_API
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source "drivers/spi/Kconfig.mcux_dspi"
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source "drivers/spi/Kconfig.nrf5_legacy"
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endif # SPI_LEGACY_API
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if !SPI_LEGACY_API
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config SPI_INTEL
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bool "Intel SPI controller driver"
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depends on CPU_MINUTEIA
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@ -299,14 +307,6 @@ config SPI_INTEL
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was formerly found on XScale chips. It can be found nowadays
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on CEXXXX Intel media controller and Quark CPU (2 of them).
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source "drivers/spi/Kconfig.mcux_dspi"
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source "drivers/spi/Kconfig.nrf5_legacy"
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endif # SPI_LEGACY_API
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if !SPI_LEGACY_API
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source "drivers/spi/Kconfig.stm32"
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endif # !SPI_LEGACY_API
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@ -6,6 +6,10 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define SYS_LOG_DOMAIN "SPI Intel"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_SPI_LEVEL
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#include <logging/sys_log.h>
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#include <errno.h>
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#include <kernel.h>
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@ -19,286 +23,243 @@
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#include <power.h>
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#include <spi.h>
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#include <spi/spi_intel.h>
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#include "spi_intel.h"
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#ifdef CONFIG_IOAPIC
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#include <drivers/ioapic.h>
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#endif
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#define SYS_LOG_DOMAIN "SPI Intel"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_SPI_LEVEL
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#include <logging/sys_log.h>
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#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
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static inline u32_t read_##__reg(u32_t addr) \
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{ \
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return sys_read##__sz(addr + __off); \
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}
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#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
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static inline void write_##__reg(u32_t data, u32_t addr) \
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{ \
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sys_write##__sz(data, addr + __off); \
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}
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DEFINE_MM_REG_WRITE(sscr0, INTEL_SPI_REG_SSCR0, 32)
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DEFINE_MM_REG_WRITE(sscr1, INTEL_SPI_REG_SSCR1, 32)
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DEFINE_MM_REG_READ(sssr, INTEL_SPI_REG_SSSR, 32)
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DEFINE_MM_REG_READ(ssdr, INTEL_SPI_REG_SSDR, 32)
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DEFINE_MM_REG_WRITE(ssdr, INTEL_SPI_REG_SSDR, 32)
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DEFINE_MM_REG_WRITE(dds_rate, INTEL_SPI_REG_DDS_RATE, 32)
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#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void set_bit_##__reg_bit(u32_t addr) \
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{ \
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sys_set_bit(addr + __reg_off, __bit); \
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}
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#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void clear_bit_##__reg_bit(u32_t addr) \
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{ \
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sys_clear_bit(addr + __reg_off, __bit); \
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}
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#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline int test_bit_##__reg_bit(u32_t addr) \
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{ \
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return sys_test_bit(addr + __reg_off, __bit); \
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}
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DEFINE_SET_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_CLEAR_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_TEST_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
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DEFINE_TEST_BIT_OP(sssr_bsy, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_BSY_BIT)
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DEFINE_CLEAR_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSCR1, INTEL_SPI_SSCR1_TIE_BIT)
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DEFINE_TEST_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSCR1, INTEL_SPI_SSCR1_TIE_BIT)
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DEFINE_CLEAR_BIT_OP(sssr_ror, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_ROR_BIT)
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#ifdef CONFIG_SPI_CS_GPIO
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#include <gpio.h>
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static inline void _spi_config_cs(struct device *dev)
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{
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const struct spi_intel_config *info = dev->config->config_info;
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struct spi_intel_data *spi = dev->driver_data;
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struct device *gpio;
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gpio = device_get_binding(info->cs_gpio_name);
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if (!gpio) {
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spi->cs_gpio_port = NULL;
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return;
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}
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gpio_pin_configure(gpio, info->cs_gpio_pin, GPIO_DIR_OUT);
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/* Default CS line to high (idling) */
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gpio_pin_write(gpio, info->cs_gpio_pin, 1);
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spi->cs_gpio_port = gpio;
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}
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static inline void _spi_control_cs(struct device *dev, int on)
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{
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const struct spi_intel_config *info = dev->config->config_info;
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struct spi_intel_data *spi = dev->driver_data;
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if (!spi->cs_gpio_port) {
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return;
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}
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gpio_pin_write(spi->cs_gpio_port, info->cs_gpio_pin, !on);
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}
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#else
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#define _spi_control_cs(...) { ; }
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#define _spi_config_cs(...) { ; }
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#endif /* CONFIG_SPI_CS_GPIO */
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static void completed(struct device *dev, u32_t error)
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{
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struct spi_intel_data *spi = dev->driver_data;
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/* if received == trans_len, then transmitted == trans_len */
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if (!(spi->received == spi->trans_len) && !error) {
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return;
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if (error) {
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goto out;
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}
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spi->error = error;
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_spi_control_cs(dev, 0);
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if (spi_context_tx_on(&spi->ctx) ||
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spi_context_rx_on(&spi->ctx)) {
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return;
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}
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out:
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write_sscr1(spi->sscr1, spi->regs);
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clear_bit_sscr0_sse(spi->regs);
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k_sem_give(&spi->device_sync_sem);
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spi_context_cs_control(&spi->ctx, false);
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SYS_LOG_DBG("SPI transaction completed %s error",
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error ? "with" : "without");
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spi_context_complete(&spi->ctx, error ? -EIO : 0);
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}
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static void pull_data(struct device *dev)
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{
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struct spi_intel_data *spi = dev->driver_data;
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u32_t cnt = 0;
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u8_t data = 0;
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while (read_sssr(spi->regs) & INTEL_SPI_SSSR_RNE) {
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data = (u8_t) read_ssdr(spi->regs);
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cnt++;
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spi->received++;
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u32_t data = read_ssdr(spi->regs);
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if ((spi->received - 1) < spi->r_buf_len) {
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*(u8_t *)(spi->rx_buf) = data;
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spi->rx_buf++;
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if (spi_context_rx_buf_on(&spi->ctx)) {
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switch (spi->dfs) {
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case 1:
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UNALIGNED_PUT(data, (u8_t *)spi->ctx.rx_buf);
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break;
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case 2:
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UNALIGNED_PUT(data, (u16_t *)spi->ctx.rx_buf);
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break;
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case 4:
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UNALIGNED_PUT(data, (u32_t *)spi->ctx.rx_buf);
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break;
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}
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spi_context_update_rx(&spi->ctx, spi->dfs, 1);
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}
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}
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SYS_LOG_DBG("Pulled: %d (total: %d)", cnt, spi->received);
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}
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static void push_data(struct device *dev)
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{
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struct spi_intel_data *spi = dev->driver_data;
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u32_t cnt = 0;
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u8_t data;
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u32_t status;
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while ((status = read_sssr(spi->regs)) & INTEL_SPI_SSSR_TNF) {
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u32_t data = 0;
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if (status & INTEL_SPI_SSSR_RFS) {
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break;
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}
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if (spi->tx_buf && (spi->transmitted < spi->t_buf_len)) {
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data = *(u8_t *)(spi->tx_buf);
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spi->tx_buf++;
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} else if (spi->transmitted < spi->trans_len) {
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data = 0;
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} else {
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/* Nothing to push anymore for now */
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break;
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if (spi_context_tx_buf_on(&spi->ctx)) {
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switch (spi->dfs) {
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case 1:
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data = UNALIGNED_GET((u8_t *)
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(spi->ctx.tx_buf));
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case 2:
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data = UNALIGNED_GET((u16_t *)
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(spi->ctx.tx_buf));
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break;
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case 4:
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data = UNALIGNED_GET((u32_t *)
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(spi->ctx.tx_buf));
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break;
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}
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}
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cnt++;
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SYS_LOG_DBG("Pushing 1 byte (total: %d)", cnt);
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write_ssdr(data, spi->regs);
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spi->transmitted++;
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spi_context_update_tx(&spi->ctx, spi->dfs, 1);
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}
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SYS_LOG_DBG("Pushed: %d (total: %d)", cnt, spi->transmitted);
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if (spi->transmitted == spi->trans_len) {
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if (!spi_context_tx_on(&spi->ctx)) {
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clear_bit_sscr1_tie(spi->regs);
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}
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}
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static int spi_intel_configure(struct device *dev,
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struct spi_config *config)
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const struct spi_config *config)
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{
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struct spi_intel_data *spi = dev->driver_data;
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u32_t flags = config->config;
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u32_t mode;
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SYS_LOG_DBG("spi_intel_configure: %p (0x%x), %p", dev, spi->regs,
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config);
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SYS_LOG_DBG("%p (0x%x), %p", dev, spi->regs, config);
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/* Check status */
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if (test_bit_sscr0_sse(spi->regs) && test_bit_sssr_bsy(spi->regs)) {
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SYS_LOG_DBG("spi_intel_configure: Controller is busy");
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return -EBUSY;
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if (spi_context_configured(&spi->ctx, config)) {
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/* Nothing to do */
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return 0;
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}
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/* Pre-configuring the registers to a clean state*/
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spi->sscr0 = spi->sscr1 = 0;
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write_sscr0(spi->sscr0, spi->regs);
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write_sscr1(spi->sscr1, spi->regs);
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if (config->operation & (SPI_OP_MODE_SLAVE || SPI_TRANSFER_LSB
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|| SPI_LINES_DUAL || SPI_LINES_QUAD ||
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SPI_LINES_OCTAL)) {
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return -EINVAL;
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}
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SYS_LOG_DBG("spi_intel_configure: WS: %d, DDS_RATE: 0x%x SCR: %d",
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SPI_WORD_SIZE_GET(flags),
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INTEL_SPI_DSS_RATE(config->max_sys_freq),
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INTEL_SPI_SSCR0_SCR(config->max_sys_freq) >> 8);
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/* Determine how many bytes are required per-frame */
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spi->dfs = SPI_WS_TO_DFS(SPI_WORD_SIZE_GET(config->operation));
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/* Pre-configuring the registers to a clean state*/
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write_sscr0(0, spi->regs);
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write_sscr1(0, spi->regs);
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/* Word size and clock rate */
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spi->sscr0 = INTEL_SPI_SSCR0_DSS(SPI_WORD_SIZE_GET(flags)) |
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INTEL_SPI_SSCR0_SCR(config->max_sys_freq);
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spi->sscr0 = INTEL_SPI_SSCR0_DSS(SPI_WORD_SIZE_GET(config->operation)) |
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INTEL_SPI_SSCR0_SCR(config->operation);
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/* Tx/Rx thresholds
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* Note: Rx thresholds needs to be 1, it does not seem to be able
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* to trigger reliably any interrupt with another value though the
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* rx fifo would be full
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*/
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spi->sscr1 |= INTEL_SPI_SSCR1_TFT(INTEL_SPI_SSCR1_TFT_DFLT) |
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INTEL_SPI_SSCR1_RFT(INTEL_SPI_SSCR1_RFT_DFLT);
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spi->sscr1 = INTEL_SPI_SSCR1_TFT(INTEL_SPI_SSCR1_TFT_DFLT) |
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INTEL_SPI_SSCR1_RFT(INTEL_SPI_SSCR1_RFT_DFLT);
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/* SPI mode */
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mode = SPI_MODE(flags);
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if (mode & SPI_MODE_CPOL) {
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) {
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spi->sscr1 |= INTEL_SPI_SSCR1_SPO;
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}
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if (mode & SPI_MODE_CPHA) {
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
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spi->sscr1 |= INTEL_SPI_SSCR1_SPH;
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}
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if (mode & SPI_MODE_LOOP) {
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if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) {
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spi->sscr1 |= INTEL_SPI_SSCR1_LBM;
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}
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/* Configuring the rate */
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write_dds_rate(INTEL_SPI_DSS_RATE(config->max_sys_freq), spi->regs);
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write_dds_rate(INTEL_SPI_DSS_RATE(config->frequency), spi->regs);
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spi_context_cs_configure(&spi->ctx);
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return 0;
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}
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static int spi_intel_transceive(struct device *dev,
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const void *tx_buf, u32_t tx_buf_len,
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void *rx_buf, u32_t rx_buf_len)
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static int transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous,
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struct k_poll_signal *signal)
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{
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struct spi_intel_data *spi = dev->driver_data;
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SYS_LOG_DBG("spi_dw_transceive: %p, %p, %u, %p, %u",
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dev, tx_buf, tx_buf_len, rx_buf, rx_buf_len);
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int ret;
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/* Check status */
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if (test_bit_sscr0_sse(spi->regs) && test_bit_sssr_bsy(spi->regs)) {
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SYS_LOG_DBG("spi_intel_transceive: Controller is busy");
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SYS_LOG_DBG("Controller is busy");
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return -EBUSY;
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}
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/* Set buffers info */
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spi->tx_buf = tx_buf;
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spi->rx_buf = rx_buf;
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spi->t_buf_len = tx_buf_len;
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spi->r_buf_len = rx_buf_len;
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spi->transmitted = 0;
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spi->received = 0;
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spi->trans_len = max(tx_buf_len, rx_buf_len);
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spi_context_lock(&spi->ctx, asynchronous, signal);
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_spi_control_cs(dev, 1);
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/* Enabling the controller */
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write_sscr0(spi->sscr0 | INTEL_SPI_SSCR0_SSE, spi->regs);
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/* Installing the registers */
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write_sscr1(spi->sscr1 | INTEL_SPI_SSCR1_RIE |
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INTEL_SPI_SSCR1_TIE, spi->regs);
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k_sem_take(&spi->device_sync_sem, K_FOREVER);
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if (spi->error) {
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spi->error = 0;
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return -EIO;
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ret = spi_intel_configure(dev, config);
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if (ret) {
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goto out;
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}
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/* Set buffers info */
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spi_context_buffers_setup(&spi->ctx, tx_bufs, rx_bufs, spi->dfs);
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spi_context_cs_control(&spi->ctx, true);
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/* Installing and Enabling the controller */
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write_sscr0(spi->sscr0 | INTEL_SPI_SSCR0_SSE, spi->regs);
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write_sscr1(spi->sscr1 | INTEL_SPI_SSCR1_RIE | INTEL_SPI_SSCR1_TIE,
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spi->regs);
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ret = spi_context_wait_for_completion(&spi->ctx);
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out:
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spi_context_release(&spi->ctx, ret);
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return ret;
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}
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static int spi_intel_transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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SYS_LOG_DBG("%p, %p, %p", dev, tx_bufs, rx_bufs);
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|
||||
return transceive(dev, config, tx_bufs, rx_bufs, false, NULL);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_ASYNC
|
||||
static int spi_intel_transceive_async(struct device *dev,
|
||||
const struct spi_config *config,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs,
|
||||
struct k_poll_signal *async)
|
||||
{
|
||||
SYS_LOG_DBG("%p, %p, %p, %p", dev, tx_bufs, rx_bufs, async);
|
||||
|
||||
return transceive(dev, config, tx_bufs, rx_bufs, true, async);
|
||||
}
|
||||
#endif /* CONFIG_SPI_ASYNC */
|
||||
|
||||
static int spi_intel_release(struct device *dev,
|
||||
const struct spi_config *config)
|
||||
{
|
||||
struct spi_intel_data *spi = dev->driver_data;
|
||||
|
||||
if (test_bit_sscr0_sse(spi->regs) && test_bit_sssr_bsy(spi->regs)) {
|
||||
SYS_LOG_DBG("Controller is busy");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
spi_context_unlock_unconditionally(&spi->ctx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spi_intel_isr(void *arg)
|
||||
void spi_intel_isr(struct device *dev)
|
||||
{
|
||||
struct device *dev = arg;
|
||||
struct spi_intel_data *spi = dev->driver_data;
|
||||
u32_t error = 0;
|
||||
u32_t status;
|
||||
|
||||
SYS_LOG_DBG("spi_intel_isr: %p", dev);
|
||||
SYS_LOG_DBG("%p", dev);
|
||||
|
||||
status = read_sssr(spi->regs);
|
||||
|
||||
if (status & INTEL_SPI_SSSR_ROR) {
|
||||
/* Unrecoverable error, ack it */
|
||||
clear_bit_sssr_ror(spi->regs);
|
||||
|
@ -320,9 +281,11 @@ out:
|
|||
}
|
||||
|
||||
static const struct spi_driver_api intel_spi_api = {
|
||||
.configure = spi_intel_configure,
|
||||
.slave_select = NULL,
|
||||
.transceive = spi_intel_transceive,
|
||||
#ifdef CONFIG_SPI_ASYNC
|
||||
.transceive_async = spi_intel_transceive_async,
|
||||
#endif /* CONFIG_SPI_ASYNC */
|
||||
.release = spi_intel_release,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
@ -354,9 +317,9 @@ static inline int spi_intel_setup(struct device *dev)
|
|||
|
||||
static void spi_intel_set_power_state(struct device *dev, u32_t power_state)
|
||||
{
|
||||
struct spi_intel_data *context = dev->driver_data;
|
||||
struct spi_intel_data *spi = dev->driver_data;
|
||||
|
||||
context->device_power_state = power_state;
|
||||
spi->device_power_state = power_state;
|
||||
}
|
||||
#else
|
||||
#define spi_intel_set_power_state(...)
|
||||
|
@ -365,7 +328,6 @@ static void spi_intel_set_power_state(struct device *dev, u32_t power_state)
|
|||
int spi_intel_init(struct device *dev)
|
||||
{
|
||||
const struct spi_intel_config *info = dev->config->config_info;
|
||||
struct spi_intel_data *spi = dev->driver_data;
|
||||
|
||||
if (!spi_intel_setup(dev)) {
|
||||
return -EPERM;
|
||||
|
@ -373,18 +335,12 @@ int spi_intel_init(struct device *dev)
|
|||
|
||||
info->config_func();
|
||||
|
||||
_spi_config_cs(dev);
|
||||
|
||||
k_sem_init(&spi->device_sync_sem, 0, UINT_MAX);
|
||||
|
||||
spi_intel_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
|
||||
|
||||
irq_enable(info->irq);
|
||||
|
||||
SYS_LOG_DBG("SPI Intel Driver initialized on device: %p", dev);
|
||||
|
||||
dev->driver_api = &intel_spi_api;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -392,9 +348,9 @@ int spi_intel_init(struct device *dev)
|
|||
|
||||
static u32_t spi_intel_get_power_state(struct device *dev)
|
||||
{
|
||||
struct spi_intel_data *context = dev->driver_data;
|
||||
struct spi_intel_data *spi = dev->driver_data;
|
||||
|
||||
return context->device_power_state;
|
||||
return spi->device_power_state;
|
||||
}
|
||||
|
||||
static int spi_intel_suspend(struct device *dev)
|
||||
|
@ -402,7 +358,7 @@ static int spi_intel_suspend(struct device *dev)
|
|||
const struct spi_intel_config *info = dev->config->config_info;
|
||||
struct spi_intel_data *spi = dev->driver_data;
|
||||
|
||||
SYS_LOG_DBG("spi_intel_suspend: %p", dev);
|
||||
SYS_LOG_DBG("%p", dev);
|
||||
|
||||
clear_bit_sscr0_sse(spi->regs);
|
||||
irq_disable(info->irq);
|
||||
|
@ -417,7 +373,7 @@ static int spi_intel_resume_from_suspend(struct device *dev)
|
|||
const struct spi_intel_config *info = dev->config->config_info;
|
||||
struct spi_intel_data *spi = dev->driver_data;
|
||||
|
||||
SYS_LOG_DBG("spi_intel_resume: %p", dev);
|
||||
SYS_LOG_DBG("%p", dev);
|
||||
|
||||
set_bit_sscr0_sse(spi->regs);
|
||||
irq_enable(info->irq);
|
||||
|
@ -457,6 +413,8 @@ static int spi_intel_device_ctrl(struct device *dev, u32_t ctrl_command,
|
|||
void spi_config_0_irq(void);
|
||||
|
||||
struct spi_intel_data spi_intel_data_port_0 = {
|
||||
SPI_CONTEXT_INIT_LOCK(spi_intel_data_port_0, ctx),
|
||||
SPI_CONTEXT_INIT_SYNC(spi_intel_data_port_0, ctx),
|
||||
.regs = SPI_INTEL_PORT_0_REGS,
|
||||
#if CONFIG_PCI
|
||||
.pci_dev.class_type = SPI_INTEL_CLASS,
|
||||
|
@ -470,17 +428,13 @@ struct spi_intel_data spi_intel_data_port_0 = {
|
|||
|
||||
const struct spi_intel_config spi_intel_config_0 = {
|
||||
.irq = SPI_INTEL_PORT_0_IRQ,
|
||||
#ifdef CONFIG_SPI_CS_GPIO
|
||||
.cs_gpio_name = CONFIG_SPI_0_CS_GPIO_PORT,
|
||||
.cs_gpio_pin = CONFIG_SPI_0_CS_GPIO_PIN,
|
||||
#endif
|
||||
.config_func = spi_config_0_irq
|
||||
};
|
||||
|
||||
/* SPI may use GPIO pin for CS, thus it needs to be initialized after GPIO */
|
||||
DEVICE_DEFINE(spi_intel_port_0, CONFIG_SPI_0_NAME, spi_intel_init,
|
||||
spi_intel_device_ctrl, &spi_intel_data_port_0,
|
||||
&spi_intel_config_0, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, NULL);
|
||||
&spi_intel_config_0, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
|
||||
&intel_spi_api);
|
||||
|
||||
void spi_config_0_irq(void)
|
||||
{
|
||||
|
@ -495,6 +449,8 @@ void spi_config_0_irq(void)
|
|||
void spi_config_1_irq(void);
|
||||
|
||||
struct spi_intel_data spi_intel_data_port_1 = {
|
||||
SPI_CONTEXT_INIT_LOCK(spi_intel_data_port_1, ctx),
|
||||
SPI_CONTEXT_INIT_SYNC(spi_intel_data_port_1, ctx),
|
||||
.regs = SPI_INTEL_PORT_1_REGS,
|
||||
#if CONFIG_PCI
|
||||
.pci_dev.class_type = SPI_INTEL_CLASS,
|
||||
|
@ -508,17 +464,13 @@ struct spi_intel_data spi_intel_data_port_1 = {
|
|||
|
||||
const struct spi_intel_config spi_intel_config_1 = {
|
||||
.irq = SPI_INTEL_PORT_1_IRQ,
|
||||
#ifdef CONFIG_SPI_CS_GPIO
|
||||
.cs_gpio_name = CONFIG_SPI_1_CS_GPIO_PORT,
|
||||
.cs_gpio_pin = CONFIG_SPI_1_CS_GPIO_PIN,
|
||||
#endif
|
||||
.config_func = spi_config_1_irq
|
||||
};
|
||||
|
||||
/* SPI may use GPIO pin for CS, thus it needs to be initialized after GPIO */
|
||||
DEVICE_DEFINE(spi_intel_port_1, CONFIG_SPI_1_NAME, spi_intel_init,
|
||||
spi_intel_device_ctrl, &spi_intel_data_port_1,
|
||||
&spi_intel_config_1, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, NULL);
|
||||
&spi_intel_config_1, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
|
||||
&intel_spi_api);
|
||||
|
||||
void spi_config_1_irq(void)
|
||||
{
|
||||
|
|
|
@ -6,13 +6,17 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SPI_INTEL_PRIV_H__
|
||||
#define __SPI_INTEL_PRIV_H__
|
||||
#ifndef __SPI_INTEL_H__
|
||||
#define __SPI_INTEL_H__
|
||||
|
||||
#include "spi_intel_regs.h"
|
||||
#include "spi_context.h"
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#include <pci/pci.h>
|
||||
#include <pci/pci_mgr.h>
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
@ -22,98 +26,77 @@ typedef void (*spi_intel_config_t)(void);
|
|||
struct spi_intel_config {
|
||||
u32_t irq;
|
||||
spi_intel_config_t config_func;
|
||||
#ifdef CONFIG_SPI_CS_GPIO
|
||||
char *cs_gpio_name;
|
||||
u32_t cs_gpio_pin;
|
||||
#endif /* CONFIG_SPI_CS_GPIO */
|
||||
};
|
||||
|
||||
struct spi_intel_data {
|
||||
struct spi_context ctx;
|
||||
u32_t regs;
|
||||
#ifdef CONFIG_PCI
|
||||
struct pci_dev_info pci_dev;
|
||||
#endif /* CONFIG_PCI */
|
||||
struct k_sem device_sync_sem;
|
||||
u8_t error;
|
||||
u8_t padding[3];
|
||||
#ifdef CONFIG_SPI_CS_GPIO
|
||||
struct device *cs_gpio_port;
|
||||
#endif /* CONFIG_SPI_CS_GPIO */
|
||||
u32_t sscr0;
|
||||
u32_t sscr1;
|
||||
const u8_t *tx_buf;
|
||||
u8_t *rx_buf;
|
||||
u32_t t_buf_len;
|
||||
u32_t r_buf_len;
|
||||
u32_t transmitted;
|
||||
u32_t received;
|
||||
u32_t trans_len;
|
||||
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
|
||||
u32_t device_power_state;
|
||||
#endif
|
||||
u8_t dfs;
|
||||
};
|
||||
|
||||
/* Registers */
|
||||
#define INTEL_SPI_REG_SSCR0 (0x00)
|
||||
#define INTEL_SPI_REG_SSCR1 (0x04)
|
||||
#define INTEL_SPI_REG_SSSR (0x08)
|
||||
#define INTEL_SPI_REG_SSDR (0x10)
|
||||
#define INTEL_SPI_REG_DDS_RATE (0x28)
|
||||
#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
|
||||
static inline u32_t read_##__reg(u32_t addr) \
|
||||
{ \
|
||||
return sys_read##__sz(addr + __off); \
|
||||
}
|
||||
#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
|
||||
static inline void write_##__reg(u32_t data, u32_t addr) \
|
||||
{ \
|
||||
sys_write##__sz(data, addr + __off); \
|
||||
}
|
||||
|
||||
#define INTEL_SPI_CLK_DIV_MASK (0x000000ff)
|
||||
#define INTEL_SPI_DDS_RATE_MASK (0xffffff00)
|
||||
DEFINE_MM_REG_WRITE(sscr0, INTEL_SPI_REG_SSCR0, 32)
|
||||
DEFINE_MM_REG_WRITE(sscr1, INTEL_SPI_REG_SSCR1, 32)
|
||||
DEFINE_MM_REG_READ(sssr, INTEL_SPI_REG_SSSR, 32)
|
||||
DEFINE_MM_REG_READ(ssdr, INTEL_SPI_REG_SSDR, 32)
|
||||
DEFINE_MM_REG_WRITE(ssdr, INTEL_SPI_REG_SSDR, 32)
|
||||
DEFINE_MM_REG_WRITE(dds_rate, INTEL_SPI_REG_DDS_RATE, 32)
|
||||
|
||||
/* SSCR0 settings */
|
||||
#define INTEL_SPI_SSCR0_DSS(__bpw) ((__bpw) - 1)
|
||||
#define INTEL_SPI_SSCR0_SSE (0x1 << 7)
|
||||
#define INTEL_SPI_SSCR0_SSE_BIT (7)
|
||||
#define INTEL_SPI_SSCR0_SCR(__msf) \
|
||||
((__msf & INTEL_SPI_CLK_DIV_MASK) << 8)
|
||||
#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
|
||||
static inline void set_bit_##__reg_bit(u32_t addr) \
|
||||
{ \
|
||||
sys_set_bit(addr + __reg_off, __bit); \
|
||||
}
|
||||
|
||||
/* SSCR1 settings */
|
||||
#define INTEL_SPI_SSCR1_TIE_BIT (1)
|
||||
#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
|
||||
static inline void clear_bit_##__reg_bit(u32_t addr) \
|
||||
{ \
|
||||
sys_clear_bit(addr + __reg_off, __bit); \
|
||||
}
|
||||
|
||||
#define INTEL_SPI_SSCR1_RIE (0x1)
|
||||
#define INTEL_SPI_SSCR1_TIE (0x1 << 1)
|
||||
#define INTEL_SPI_SSCR1_LBM (0x1 << 2)
|
||||
#define INTEL_SPI_SSCR1_SPO (0x1 << 3)
|
||||
#define INTEL_SPI_SSCR1_SPH (0x1 << 4)
|
||||
#define INTEL_SPI_SSCR1_TFT_MASK (0x1f << 6)
|
||||
#define INTEL_SPI_SSCR1_TFT(__tft) \
|
||||
(((__tft) - 1) << 6)
|
||||
#define INTEL_SPI_SSCR1_RFT_MASK (0x1f << 11)
|
||||
#define INTEL_SPI_SSCR1_RFT(__rft) \
|
||||
(((__rft) - 1) << 11)
|
||||
#define INTEL_SPI_SSCR1_EFWR (0x1 << 16)
|
||||
#define INTEL_SPI_SSCR1_STRF (0x1 << 17)
|
||||
#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
|
||||
static inline int test_bit_##__reg_bit(u32_t addr) \
|
||||
{ \
|
||||
return sys_test_bit(addr + __reg_off, __bit); \
|
||||
}
|
||||
|
||||
#define INTEL_SPI_SSCR1_TFT_DFLT (8)
|
||||
#define INTEL_SPI_SSCR1_RFT_DFLT (1)
|
||||
DEFINE_SET_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
|
||||
DEFINE_CLEAR_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
|
||||
DEFINE_TEST_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
|
||||
DEFINE_TEST_BIT_OP(sssr_bsy, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_BSY_BIT)
|
||||
DEFINE_CLEAR_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSCR1, INTEL_SPI_SSCR1_TIE_BIT)
|
||||
DEFINE_TEST_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSCR1, INTEL_SPI_SSCR1_TIE_BIT)
|
||||
DEFINE_CLEAR_BIT_OP(sssr_ror, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_ROR_BIT)
|
||||
|
||||
/* SSSR settings */
|
||||
#define INTEL_SPI_SSSR_TNF (0x4)
|
||||
#define INTEL_SPI_SSSR_RNE (0x8)
|
||||
#define INTEL_SPI_SSSR_TFS (0x20)
|
||||
#define INTEL_SPI_SSSR_RFS (0x40)
|
||||
#define INTEL_SPI_SSSR_ROR (0x80)
|
||||
#define INTEL_SPI_SSSR_TFL_MASK (0x1f << 8)
|
||||
#define INTEL_SPI_SSSR_TFL_EMPTY (0x00)
|
||||
#define INTEL_SPI_SSSR_RFL_MASK (0x1f << 13)
|
||||
#define INTEL_SPI_SSSR_RFL_EMPTY (0x1f)
|
||||
/* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
|
||||
* These are the bits were when you divide by 8, you keep the result as it is.
|
||||
* For all the other ones, 4 to 7, 9 to 15, etc... you need a +1,
|
||||
* since on such division it takes only the result above 0
|
||||
*/
|
||||
#define SPI_WS_TO_DFS(__bpw) (((__bpw) & ~0x38) ? \
|
||||
(((__bpw) / 8) + 1) : \
|
||||
((__bpw) / 8))
|
||||
|
||||
#define INTEL_SPI_SSSR_TFL(__status) \
|
||||
((__status & INTEL_SPI_SSSR_TFL_MASK) >> 8)
|
||||
#define INTEL_SPI_SSSR_RFL(__status) \
|
||||
((__status & INTEL_SPI_SSSR_RFL_MASK) >> 13)
|
||||
|
||||
#define INTEL_SPI_SSSR_BSY_BIT (4)
|
||||
#define INTEL_SPI_SSSR_ROR_BIT (7)
|
||||
|
||||
/* DSS_RATE settings */
|
||||
#define INTEL_SPI_DSS_RATE(__msf) \
|
||||
((__msf & (INTEL_SPI_DDS_RATE_MASK)) >> 8)
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SPI_INTEL_PRIV_H__ */
|
||||
#endif /* __SPI_INTEL_H__ */
|
||||
|
|
80
drivers/spi/spi_intel_regs.h
Normal file
80
drivers/spi/spi_intel_regs.h
Normal file
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SPI_INTEL_REGS_H__
|
||||
#define __SPI_INTEL_REGS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Intel's SPI driver registers definition */
|
||||
|
||||
/* Registers */
|
||||
#define INTEL_SPI_REG_SSCR0 (0x00)
|
||||
#define INTEL_SPI_REG_SSCR1 (0x04)
|
||||
#define INTEL_SPI_REG_SSSR (0x08)
|
||||
#define INTEL_SPI_REG_SSDR (0x10)
|
||||
#define INTEL_SPI_REG_DDS_RATE (0x28)
|
||||
|
||||
#define INTEL_SPI_CLK_DIV_MASK (0x000000ff)
|
||||
#define INTEL_SPI_DDS_RATE_MASK (0xffffff00)
|
||||
|
||||
/* SSCR0 settings */
|
||||
#define INTEL_SPI_SSCR0_DSS(__bpw) ((__bpw) - 1)
|
||||
#define INTEL_SPI_SSCR0_SSE (0x1 << 7)
|
||||
#define INTEL_SPI_SSCR0_SSE_BIT (7)
|
||||
#define INTEL_SPI_SSCR0_SCR(__msf) \
|
||||
((__msf & INTEL_SPI_CLK_DIV_MASK) << 8)
|
||||
|
||||
/* SSCR1 settings */
|
||||
#define INTEL_SPI_SSCR1_TIE_BIT (1)
|
||||
|
||||
#define INTEL_SPI_SSCR1_RIE (0x1)
|
||||
#define INTEL_SPI_SSCR1_TIE (0x1 << 1)
|
||||
#define INTEL_SPI_SSCR1_LBM (0x1 << 2)
|
||||
#define INTEL_SPI_SSCR1_SPO (0x1 << 3)
|
||||
#define INTEL_SPI_SSCR1_SPH (0x1 << 4)
|
||||
#define INTEL_SPI_SSCR1_TFT_MASK (0x1f << 6)
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#define INTEL_SPI_SSCR1_TFT(__tft) \
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(((__tft) - 1) << 6)
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||||
#define INTEL_SPI_SSCR1_RFT_MASK (0x1f << 11)
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#define INTEL_SPI_SSCR1_RFT(__rft) \
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(((__rft) - 1) << 11)
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#define INTEL_SPI_SSCR1_EFWR (0x1 << 16)
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#define INTEL_SPI_SSCR1_STRF (0x1 << 17)
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||||
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||||
#define INTEL_SPI_SSCR1_TFT_DFLT (8)
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#define INTEL_SPI_SSCR1_RFT_DFLT (1)
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||||
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||||
/* SSSR settings */
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||||
#define INTEL_SPI_SSSR_TNF (0x4)
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#define INTEL_SPI_SSSR_RNE (0x8)
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||||
#define INTEL_SPI_SSSR_TFS (0x20)
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||||
#define INTEL_SPI_SSSR_RFS (0x40)
|
||||
#define INTEL_SPI_SSSR_ROR (0x80)
|
||||
#define INTEL_SPI_SSSR_TFL_MASK (0x1f << 8)
|
||||
#define INTEL_SPI_SSSR_TFL_EMPTY (0x00)
|
||||
#define INTEL_SPI_SSSR_RFL_MASK (0x1f << 13)
|
||||
#define INTEL_SPI_SSSR_RFL_EMPTY (0x1f)
|
||||
|
||||
#define INTEL_SPI_SSSR_TFL(__status) \
|
||||
((__status & INTEL_SPI_SSSR_TFL_MASK) >> 8)
|
||||
#define INTEL_SPI_SSSR_RFL(__status) \
|
||||
((__status & INTEL_SPI_SSSR_RFL_MASK) >> 13)
|
||||
|
||||
#define INTEL_SPI_SSSR_BSY_BIT (4)
|
||||
#define INTEL_SPI_SSSR_ROR_BIT (7)
|
||||
|
||||
/* DSS_RATE settings */
|
||||
#define INTEL_SPI_DSS_RATE(__msf) \
|
||||
((__msf & (INTEL_SPI_DDS_RATE_MASK)) >> 8)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SPI_INTEL_REGS_H__ */
|
|
@ -1,53 +0,0 @@
|
|||
/* spi_intel.h - Intel's SPI controller driver utilities */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SPI_INTEL_H__
|
||||
#define __SPI_INTEL_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* SPI Maximum supported system frequencies */
|
||||
#define SPI_MAX_CLK_FREQ_25MHZ ((0x800000 << 8))
|
||||
#define SPI_MAX_CLK_FREQ_20MHz ((0x666666 << 8) | 1)
|
||||
#define SPI_MAX_CLK_FREQ_166667KHZ ((0x800000 << 8) | 2)
|
||||
#define SPI_MAX_CLK_FREQ_13333KHZ ((0x666666 << 8) | 2)
|
||||
#define SPI_MAX_CLK_FREQ_12500KHZ ((0x200000 << 8))
|
||||
#define SPI_MAX_CLK_FREQ_10MHZ ((0x800000 << 8) | 4)
|
||||
#define SPI_MAX_CLK_FREQ_8MHZ ((0x666666 << 8) | 4)
|
||||
#define SPI_MAX_CLK_FREQ_6250HZ ((0x400000 << 8) | 3)
|
||||
#define SPI_MAX_CLK_FREQ_5MHZ ((0x400000 << 8) | 4)
|
||||
#define SPI_MAX_CLK_FREQ_4MHZ ((0x666666 << 8) | 9)
|
||||
#define SPI_MAX_CLK_FREQ_3125KHZ ((0x80000 << 8))
|
||||
#define SPI_MAX_CLK_FREQ_2500KHZ ((0x400000 << 8) | 9)
|
||||
#define SPI_MAX_CLK_FREQ_2MHZ ((0x666666 << 8) | 19)
|
||||
#define SPI_MAX_CLK_FREQ_1563KHZ ((0x40000 << 8))
|
||||
#define SPI_MAX_CLK_FREQ_1250KHZ ((0x200000 << 8) | 9)
|
||||
#define SPI_MAX_CLK_FREQ_1MHZ ((0x400000 << 8) | 24)
|
||||
#define SPI_MAX_CLK_FREQ_800KHZ ((0x666666 << 8) | 49)
|
||||
#define SPI_MAX_CLK_FREQ_781KHZ ((0x20000 << 8))
|
||||
#define SPI_MAX_CLK_FREQ_625KHZ ((0x200000 << 8) | 19)
|
||||
#define SPI_MAX_CLK_FREQ_500KHZ ((0x400000 << 8) | 49)
|
||||
#define SPI_MAX_CLK_FREQ_400KHZ ((0x666666 << 8) | 99)
|
||||
#define SPI_MAX_CLK_FREQ_390KHZ ((0x10000 << 8))
|
||||
#define SPI_MAX_CLK_FREQ_250KHZ ((0x400000 << 8) | 99)
|
||||
#define SPI_MAX_CLK_FREQ_200KHZ ((0x666666 << 8) | 199)
|
||||
#define SPI_MAX_CLK_FREQ_195KHZ ((0x8000 << 8))
|
||||
#define SPI_MAX_CLK_FREQ_125KHZ ((0x100000 << 8) | 49)
|
||||
#define SPI_MAX_CLK_FREQ_100KHZ ((0x200000 << 8) | 124)
|
||||
#define SPI_MAX_CLK_FREQ_50KHZ ((0x100000 << 8) | 124)
|
||||
#define SPI_MAX_CLK_FREQ_20KHZ ((0x80000 << 8) | 124)
|
||||
#define SPI_MAX_CLK_FREQ_10KHZ ((0x20000 << 8) | 77)
|
||||
#define SPI_MAX_CLK_FREQ_5KHZ ((0x20000 << 8) | 154)
|
||||
#define SPI_MAX_CLK_FREQ_1KHZ ((0x8000 << 8) | 194)
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SPI_INTEL_H__ */
|
Loading…
Add table
Add a link
Reference in a new issue