Add a driver for the VIRTIO SPI controller device (virtio spec 1.4,
section 5.21), letting a Zephyr guest drive a SPI bus exposed by a
hypervisor or a vhost-user backend.
The device carries a single transfer per request, so a transceive call
is split into one request per contiguous chunk of the buffer sets, with
cs_change holding the chip select asserted in between. The controller
capabilities are read from the device configuration space at init and
checked against the SPI configuration. Every request is a round trip to
the device, so the SPI API can only be used from a thread.
Assisted-by: Claude Code:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Introduce polling-based SPI driver for the NXP Kinetis-L series.
The driver implements spi_context and utilizes standard Zephyr
Clock Control and Pinctrl subsystems.
Signed-off-by: Gabriel Ivo <gabriel.bozi@usp.br>
The RTS5817's SPI is based on snps,designware-spi, but it's not
entirely the same, so DW spi drivers cannot be used directly.
The rts5817 spi driver uses some DW spi code:
1. pin_ctrl is handled in the spi_dw.c code initialization.
2. Several APIs defined in spi_dw.h is used by spi_rts5817.c.
Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
Add a driver for the Generic Quad SPI hardware that is part of the
Xilinx MPSoC. This is mostly commonly used with QSPI flash devices which
are also used for initial image loading, but can also be used with other
SPI devices.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add SPI driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Master and Slave operation modes
- Polling, Interrupt, and DMA transfer modes
- Transmit (TX) and Receive (RX) functionality
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add support for the SPI module on TI’s MSPM0 MCUs.
The driver supports master mode transfers with configurable
frame size (4–16 bits), clock polarity/phase, bit order.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
Refactor the nrf_spim device driver to share the common code between
the nrf_spim_rtio implementation.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Rename Kconfig options and internal macros to remove "CAT1" specificity,
making the driver more generic for the Infineon family. This is a
non-functional change to prepare for PSoC 4 support.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
We converted the QMSPI-LDMA driver to linux style with a local
register header in the driver folder. This is part of the long
term plan to remove the MEC5 HAL and have common drivers for
as many SoC's as possible. QMSPI register definitions are in
the SoC layer to be shared with other drivers (MSPI). The driver
was also updated based on changes in the SPI config structure.
The lastest SPI config structure changes force hardware controlled
chip selects and GPIO controlled chip selects to be mutually exclusive.
NOTE: driver works with the flash driver sample
and passes the common flash driver test.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Before that commit spi was not available for the soc sy1xx.
With this commit a basic usage of spi is possible.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Fin Maaß <f.maass@vogl-electronic.com>
- Add SPI driver for Microchip SERCOM g1
- Add and update Kconfig files to support the driver
- Update CMakeLists.txt to include the new driver
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
The `ll` part of driver's file name indicates that the implementation uses
the STM32Cube Low Level ("LL") library, which is not interesting because
there is only *one* STM32 driver implementation anyways. Addtionnally, the
presence of `ll` among STM32 drivers is not consistent.
Get rid of it for this class's driver to match most other STM32 drivers.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Removing references to infineon,cat1-spi-pdl from the device tree files.
Updates the driver bindings and driver file to look at the
infineon,cat1-spi binding and uses a Kconfig option to select Legacy HAL
implementation instead.
See https://github.com/zephyrproject-rtos/zephyr/pull/98035 for context.
Signed-off-by: John Batch <john.batch@infineon.com>
Add SPI driver support for Renesas RZN2L, T2M
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
The Egis ET171 SPI controller was based on Andes ATCSPI200,
but has since been modified. In particular, the WrTranCnt and RdTranCnt
fields from the SPI Transfer Control Register have been moved to dedicated
Wr_Tran_Cnt and Rd_Tran_Cnt registers.
Signed-off-by: jacob kung <jacob.kung@egistec.com>
This patch adds the initial support for the OMAP Multi-Channel SPI. Some
things should be noted however:
- DMA xfers are not supported yet. Only PIO is supported as of now.
- Multi-Channel controller is not supported yet. Only single-channel
controller mode is supported, this means that the controller can xfer
messages with one slave at a time.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Initial commit for SPI driver support on RSK_RX130@512KB board
with RSPI module
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Minh Tang <minh.tang.ue@bp.renesas.com>
SPI driver for Microchip MEC5 HAL based QSPI controller. QSPI
hardware supports full duplex, dual, and quad operation. MEC5
QSPI controller also includes three local DMA channels per
direction to off load firmware. The driver API supports full
or half-duplex. Due to QSPI hardware not supporting one wire
half-duplex, this driver supports full-duplex only. QSPI hardware
design requires it to control chip select and current hardware
supports up to two chip selects. Zephyr's SPI DT macros store the
child SPI device's reg properity as the "slave" member of the SPI
configuration structure. The driver uses the "slave" value as the
chip select. Additional timing settings specific to SPI flash devices
are in a new SPI device YAM file: "microchip,mec5-qspi-device.yaml"
which includes the standard "spi-device.yaml". If the new YAML is not
used, the QSPI controller will use default timing values for chip
select and I/O line taps.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add support for SPI to cc23x0 SoC. Only controller mode is implemented.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Move this driver to its own subfolder to organize it
since there will be new files added for this hardware.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Add SPI driver support for RA
- RA2A1 not support slave select keeping level so disable it
in Kconfig
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
