drivers: spi: Add shim for nrfx SPI driver
This adds a translation layer to make the nrfx driver for the legacy (i.e. without EasyDMA) nRF SPI peripheral accessible via the updated Zephyr's API of the SPI driver. Configuration files are already prepared for adding support for SPIM (Master with EasyDMA) and SPIS (Slave with EasyDMA) peripherals. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek
Carles Cufí
parent
09dd5e9b22
commit
00397c65bc
9 changed files with 611 additions and 60 deletions
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@ -7,6 +7,7 @@ else()
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zephyr_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
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zephyr_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
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zephyr_sources_ifdef(CONFIG_SPI_SAM0 spi_sam0.c)
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zephyr_sources_ifdef(CONFIG_NRFX_SPI spi_nrfx_spi.c)
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endif()
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zephyr_sources_ifdef(CONFIG_USERSPACE spi_handlers.c)
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@ -313,6 +313,8 @@ source "drivers/spi/Kconfig.mcux_dspi"
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source "drivers/spi/Kconfig.sam0"
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source "drivers/spi/Kconfig.nrfx"
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endif # !SPI_LEGACY_API
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endif # SPI
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210
drivers/spi/Kconfig.nrfx
Normal file
210
drivers/spi/Kconfig.nrfx
Normal file
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@ -0,0 +1,210 @@
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# Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig SPI_NRFX
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bool "nRF SPI nrfx drivers"
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depends on SOC_FAMILY_NRF
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help
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Enable support for nrfx SPI drivers for nRF MCU series.
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Peripherals with the same instance ID cannot be used together,
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e.g. SPI_0 and I2C_0. You may need to disable I2C_0 or I2C_1.
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if SPI_NRFX
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# Nordic TWIx0 and SPIx0 instances can not be used at the same time
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if SPI_0 && !I2C_0
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choice
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prompt "SPI Port 0 Driver type"
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optional
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config SPI_0_NRF_SPI
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bool "nRF SPI 0"
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depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF51X
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select NRFX_SPI
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help
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Enable nRF SPI Master without EasyDMA on port 0
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config SPI_0_NRF_SPIM
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bool "nRF SPIM 0"
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depends on SOC_SERIES_NRF52X
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select NRFX_SPIM
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help
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Enable nRF SPI Master with EasyDMA on port 0
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config SPI_0_NRF_SPIS
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bool "nRF SPIS 0"
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depends on SOC_SERIES_NRF52X
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select NRFX_SPIS
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help
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Enable nRF SPI Slave with EasyDMA on port 0
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endchoice
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if SPI_0_NRF_SPI || SPI_0_NRF_SPIM || SPI_0_NRF_SPIS
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config SPI_0_NRF_SCK_PIN
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int "SCK pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for SCK
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config SPI_0_NRF_MOSI_PIN
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int "MOSI pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MOSI
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config SPI_0_NRF_MISO_PIN
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int "MISO pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MISO
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config SPI_0_NRF_ORC
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hex "Over-read Character"
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range 0x00 0xff
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default 0xff
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help
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Over-read character. Character clocked out after an over-read
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of the transmit buffer.
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endif # SPI_0_NRF_SPI || SPI_0_NRF_SPIM || SPI_0_NRF_SPIS
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endif # SPI_0 && !I2C_0
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# Nordic TWIx1 and SPIx1 instances can not be used at the same time
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if SPI_1 && !I2C_1
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choice
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prompt "SPI Port 1 Driver type"
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optional
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config SPI_1_NRF_SPI
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bool "nRF SPI 1"
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depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF51X
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select NRFX_SPI
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help
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Enable nRF SPI Master without EasyDMA on port 1
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config SPI_1_NRF_SPIM
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bool "nRF SPIM 1"
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depends on SOC_SERIES_NRF52X
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select NRFX_SPIM
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help
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Enable nRF SPI Master with EasyDMA on port 1
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config SPI_1_NRF_SPIS
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bool "nRF SPIS 1"
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depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF51X
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select NRFX_SPIS
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help
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Enable nRF SPI Slave with EasyDMA on port 1
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endchoice
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if SPI_1_NRF_SPI || SPI_1_NRF_SPIM || SPI_1_NRF_SPIS
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config SPI_1_NRF_SCK_PIN
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int "SCK pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for SCK
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config SPI_1_NRF_MOSI_PIN
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int "MOSI pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MOSI
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config SPI_1_NRF_MISO_PIN
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int "MISO pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MISO
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config SPI_1_NRF_ORC
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hex "Over-read Character"
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range 0x00 0xff
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default 0xff
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help
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Over-read character. Character clocked out after an over-read
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of the transmit buffer.
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endif # SPI_1_NRF_SPI || SPI_1_NRF_SPIM || SPI_1_NRF_SPIS
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endif # SPI_1 && !I2C_1
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if SPI_2
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choice
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prompt "SPI Port 2 Driver type"
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optional
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config SPI_2_NRF_SPI
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bool "nRF SPI 2"
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depends on SOC_SERIES_NRF52X
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select NRFX_SPI
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help
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Enable nRF SPI Master without EasyDMA on port 2
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config SPI_2_NRF_SPIM
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bool "nRF SPIM 2"
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depends on SOC_SERIES_NRF52X
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select NRFX_SPIM
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help
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Enable nRF SPI Master with EasyDMA on port 2
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config SPI_2_NRF_SPIS
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bool "nRF SPIS 2"
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depends on SOC_SERIES_NRF52X
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select NRFX_SPIS
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help
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Enable nRF SPI Slave with EasyDMA on port 2
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endchoice
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if SPI_2_NRF_SPI || SPI_2_NRF_SPIM || SPI_2_NRF_SPIS
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config SPI_2_NRF_SCK_PIN
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int "SCK pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for SCK
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config SPI_2_NRF_MOSI_PIN
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int "MOSI pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MOSI
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config SPI_2_NRF_MISO_PIN
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int "MISO pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MISO
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config SPI_2_NRF_ORC
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hex "Over-read Character"
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range 0x00 0xff
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default 0xff
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help
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Over-read character. Character clocked out after an over-read
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of the transmit buffer.
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endif # SPI_2_NRF_SPI || SPI_2_NRF_SPIM || SPI_2_NRF_SPIS
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endif # SPI_2
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endif # SPI_NRFX
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328
drivers/spi/spi_nrfx_spi.c
Normal file
328
drivers/spi/spi_nrfx_spi.c
Normal file
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@ -0,0 +1,328 @@
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/*
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* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <spi.h>
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#include <nrfx_spi.h>
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#define SYS_LOG_DOMAIN "spi_nrfx_spi"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_SPI_LEVEL
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#include <logging/sys_log.h>
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#include "spi_context.h"
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struct spi_nrfx_data {
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struct spi_context ctx;
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size_t chunk_len;
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bool busy;
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};
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struct spi_nrfx_config {
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nrfx_spi_t spi;
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};
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static inline struct spi_nrfx_data *get_dev_data(struct device *dev)
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{
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return dev->driver_data;
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}
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static inline const struct spi_nrfx_config *get_dev_config(struct device *dev)
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{
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return dev->config->config_info;
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}
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static inline nrf_spi_frequency_t get_nrf_spi_frequency(u32_t frequency)
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{
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/* Get the highest supported frequency not exceeding the requested one.
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*/
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if (frequency < 250000) {
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return NRF_SPI_FREQ_125K;
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} else if (frequency < 500000) {
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return NRF_SPI_FREQ_250K;
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} else if (frequency < 1000000) {
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return NRF_SPI_FREQ_500K;
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} else if (frequency < 2000000) {
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return NRF_SPI_FREQ_1M;
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} else if (frequency < 4000000) {
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return NRF_SPI_FREQ_2M;
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} else if (frequency < 8000000) {
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return NRF_SPI_FREQ_4M;
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} else {
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return NRF_SPI_FREQ_8M;
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}
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}
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static inline nrf_spi_mode_t get_nrf_spi_mode(u16_t operation)
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{
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if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
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if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
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return NRF_SPI_MODE_3;
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} else {
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return NRF_SPI_MODE_2;
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}
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} else {
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if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
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return NRF_SPI_MODE_1;
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} else {
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return NRF_SPI_MODE_0;
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}
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}
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}
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static inline nrf_spi_bit_order_t get_nrf_spi_bit_order(u16_t operation)
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{
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if (operation & SPI_TRANSFER_LSB) {
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return NRF_SPI_BIT_ORDER_LSB_FIRST;
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} else {
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return NRF_SPI_BIT_ORDER_MSB_FIRST;
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}
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}
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static int configure(struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_context *ctx = &get_dev_data(dev)->ctx;
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const nrfx_spi_t *spi = &get_dev_config(dev)->spi;
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if (spi_context_configured(ctx, spi_cfg)) {
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/* Already configured. No need to do it again. */
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return 0;
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}
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if (spi_cfg->operation & SPI_OP_MODE_SLAVE) {
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SYS_LOG_ERR("Slave mode is not supported for %s",
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dev->config->name);
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return -EINVAL;
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}
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if (spi_cfg->operation & SPI_MODE_LOOP) {
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SYS_LOG_ERR("Loopback mode is not supported");
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return -EINVAL;
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}
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if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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SYS_LOG_ERR("Only single line mode is supported");
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return -EINVAL;
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}
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if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
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SYS_LOG_ERR("Word sizes other than 8 bits"
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" are not supported");
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return -EINVAL;
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}
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if (spi_cfg->frequency < 125000) {
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SYS_LOG_ERR("Frequencies lower than 125 kHz are not supported");
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return -EINVAL;
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}
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ctx->config = spi_cfg;
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spi_context_cs_configure(ctx);
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nrf_spi_configure(spi->p_reg,
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get_nrf_spi_mode(spi_cfg->operation),
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get_nrf_spi_bit_order(spi_cfg->operation));
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nrf_spi_frequency_set(spi->p_reg,
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get_nrf_spi_frequency(spi_cfg->frequency));
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return 0;
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}
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static void transfer_next_chunk(struct device *dev)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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struct spi_context *ctx = &dev_data->ctx;
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int error = 0;
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size_t chunk_len = spi_context_longest_current_buf(ctx);
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if (chunk_len > 0) {
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const nrfx_spi_xfer_desc_t xfer_desc = {
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.p_tx_buffer = ctx->tx_buf,
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.tx_length = spi_context_tx_buf_on(ctx) ? chunk_len : 0,
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.p_rx_buffer = ctx->rx_buf,
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.rx_length = spi_context_rx_buf_on(ctx) ? chunk_len : 0,
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};
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dev_data->chunk_len = chunk_len;
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nrfx_err_t result = nrfx_spi_xfer(&get_dev_config(dev)->spi,
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&xfer_desc, 0);
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if (result == NRFX_SUCCESS) {
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return;
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}
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error = -EIO;
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}
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spi_context_cs_control(ctx, false);
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SYS_LOG_DBG("Transaction finished with status %d", error);
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spi_context_complete(ctx, error);
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dev_data->busy = false;
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}
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static int transceive(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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int error;
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error = configure(dev, spi_cfg);
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if (error == 0) {
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dev_data->busy = true;
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spi_context_buffers_setup(&dev_data->ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(&dev_data->ctx, true);
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transfer_next_chunk(dev);
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error = spi_context_wait_for_completion(&dev_data->ctx);
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}
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spi_context_release(&dev_data->ctx, error);
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return error;
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}
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static int spi_nrfx_transceive(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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spi_context_lock(&get_dev_data(dev)->ctx, false, NULL);
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs);
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_nrfx_transceive_async(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *async)
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{
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spi_context_lock(&get_dev_data(dev)->ctx, true, async);
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs);
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int spi_nrfx_release(struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
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return -EINVAL;
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}
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if (dev_data->busy) {
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(&dev_data->ctx);
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return 0;
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}
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static const struct spi_driver_api spi_nrfx_driver_api = {
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.transceive = spi_nrfx_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_nrfx_transceive_async,
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#endif
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.release = spi_nrfx_release,
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};
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static void event_handler(const nrfx_spi_evt_t *p_event, void *p_context)
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{
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struct device *dev = p_context;
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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if (p_event->type == NRFX_SPI_EVENT_DONE) {
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spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
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spi_context_update_rx(&dev_data->ctx, 1, dev_data->chunk_len);
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transfer_next_chunk(dev);
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}
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}
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|
||||
static int init_spi(struct device *dev, const nrfx_spi_config_t *config)
|
||||
{
|
||||
/* This sets only default values of frequency, mode and bit order.
|
||||
* The proper ones are set in configure() when a transfer is started.
|
||||
*/
|
||||
nrfx_err_t result = nrfx_spi_init(&get_dev_config(dev)->spi,
|
||||
config,
|
||||
event_handler,
|
||||
dev);
|
||||
if (result != NRFX_SUCCESS) {
|
||||
SYS_LOG_ERR("Failed to initialize device: %s",
|
||||
dev->config->name);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
spi_context_unlock_unconditionally(&get_dev_data(dev)->ctx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void spi_isr(void *irq_handler)
|
||||
{
|
||||
((nrfx_irq_handler_t)irq_handler)();
|
||||
}
|
||||
|
||||
/* In Nordic SoCs the IRQ number assigned to a peripheral is equal to the ID
|
||||
* of the block of 0x1000 bytes in the peripheral address space assigned to
|
||||
* this peripheral. See the chapter "Peripheral interface" (sections "Peripheral
|
||||
* ID" and "Interrupts") in the product specification of a given SoC.
|
||||
*/
|
||||
#define NRF_SPI_IRQ_NUMBER(idx) (uint8_t)((uint32_t)NRF_SPI##idx >> 12u)
|
||||
|
||||
#define SPI_NRFX_SPI_DEVICE(idx) \
|
||||
static int spi_##idx##_init(struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(NRF_SPI_IRQ_NUMBER(idx), \
|
||||
CONFIG_SPI_##idx##_IRQ_PRI, \
|
||||
spi_isr, nrfx_spi_##idx##_irq_handler, 0); \
|
||||
const nrfx_spi_config_t config = { \
|
||||
.sck_pin = CONFIG_SPI_##idx##_NRF_SCK_PIN, \
|
||||
.mosi_pin = CONFIG_SPI_##idx##_NRF_MOSI_PIN, \
|
||||
.miso_pin = CONFIG_SPI_##idx##_NRF_MISO_PIN, \
|
||||
.ss_pin = NRFX_SPI_PIN_NOT_USED, \
|
||||
.orc = CONFIG_SPI_##idx##_NRF_ORC, \
|
||||
.frequency = NRF_SPI_FREQ_4M, \
|
||||
.mode = NRF_SPI_MODE_0, \
|
||||
.bit_order = NRF_SPI_BIT_ORDER_MSB_FIRST, \
|
||||
}; \
|
||||
return init_spi(dev, &config); \
|
||||
} \
|
||||
static struct spi_nrfx_data spi_##idx##_data = { \
|
||||
SPI_CONTEXT_INIT_LOCK(spi_##idx##_data, ctx), \
|
||||
SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx), \
|
||||
.busy = false, \
|
||||
}; \
|
||||
static const struct spi_nrfx_config spi_##idx##_config = { \
|
||||
.spi = NRFX_SPI_INSTANCE(idx), \
|
||||
}; \
|
||||
DEVICE_AND_API_INIT(spi_##idx, CONFIG_SPI_##idx##_NAME, \
|
||||
spi_##idx##_init, \
|
||||
&spi_##idx##_data, \
|
||||
&spi_##idx##_config, \
|
||||
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
|
||||
&spi_nrfx_driver_api)
|
||||
|
||||
#ifdef CONFIG_SPI_0_NRF_SPI
|
||||
SPI_NRFX_SPI_DEVICE(0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPI_1_NRF_SPI
|
||||
SPI_NRFX_SPI_DEVICE(1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPI_2_NRF_SPI
|
||||
SPI_NRFX_SPI_DEVICE(2);
|
||||
#endif
|
||||
|
|
@ -19,6 +19,7 @@ if(CONFIG_HAS_NRFX)
|
|||
zephyr_sources_ifdef(CONFIG_NRFX_SAADC nrfx/drivers/src/nrfx_saadc.c)
|
||||
zephyr_sources_ifdef(CONFIG_NRFX_SPI nrfx/drivers/src/nrfx_spi.c)
|
||||
zephyr_sources_ifdef(CONFIG_NRFX_SPIM nrfx/drivers/src/nrfx_spim.c)
|
||||
zephyr_sources_ifdef(CONFIG_NRFX_SPIS nrfx/drivers/src/nrfx_spis.c)
|
||||
zephyr_sources_ifdef(CONFIG_NRFX_TWI nrfx/drivers/src/nrfx_twi.c)
|
||||
zephyr_sources_ifdef(CONFIG_NRFX_TWIM nrfx/drivers/src/nrfx_twim.c)
|
||||
zephyr_sources_ifdef(CONFIG_NRFX_UART nrfx/drivers/src/nrfx_uart.c)
|
||||
|
|
|
|||
|
|
@ -9,3 +9,12 @@ config HAS_NORDIC_DRIVERS
|
|||
|
||||
config HAS_NRFX
|
||||
bool
|
||||
|
||||
config NRFX_SPI
|
||||
bool
|
||||
|
||||
config NRFX_SPIM
|
||||
bool
|
||||
|
||||
config NRFX_SPIS
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -877,14 +877,14 @@
|
|||
|
||||
// <e> NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
|
||||
//==========================================================
|
||||
#ifndef NRFX_SPIS_ENABLED
|
||||
#define NRFX_SPIS_ENABLED 0
|
||||
#ifdef CONFIG_NRFX_SPIS
|
||||
#define NRFX_SPIS_ENABLED 1
|
||||
#endif
|
||||
// <q> NRFX_SPIS1_ENABLED - Enable SPIS1 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIS1_ENABLED
|
||||
#define NRFX_SPIS1_ENABLED 0
|
||||
#ifdef CONFIG_SPI_1_NRF_SPIS
|
||||
#define NRFX_SPIS1_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <o> NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
|
||||
|
|
@ -967,21 +967,21 @@
|
|||
|
||||
// <e> NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
|
||||
//==========================================================
|
||||
#ifndef NRFX_SPI_ENABLED
|
||||
#define NRFX_SPI_ENABLED 0
|
||||
#ifdef CONFIG_NRFX_SPI
|
||||
#define NRFX_SPI_ENABLED 1
|
||||
#endif
|
||||
// <q> NRFX_SPI0_ENABLED - Enable SPI0 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPI0_ENABLED
|
||||
#define NRFX_SPI0_ENABLED 0
|
||||
#ifdef CONFIG_SPI_0_NRF_SPI
|
||||
#define NRFX_SPI0_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPI1_ENABLED - Enable SPI1 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPI1_ENABLED
|
||||
#define NRFX_SPI1_ENABLED 0
|
||||
#ifdef CONFIG_SPI_1_NRF_SPI
|
||||
#define NRFX_SPI1_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <o> NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration.
|
||||
|
|
|
|||
|
|
@ -1605,28 +1605,28 @@
|
|||
|
||||
// <e> NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
|
||||
//==========================================================
|
||||
#ifndef NRFX_SPIM_ENABLED
|
||||
#define NRFX_SPIM_ENABLED 0
|
||||
#ifdef CONFIG_NRFX_SPIM
|
||||
#define NRFX_SPIM_ENABLED 1
|
||||
#endif
|
||||
// <q> NRFX_SPIM0_ENABLED - Enable SPIM0 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIM0_ENABLED
|
||||
#define NRFX_SPIM0_ENABLED 0
|
||||
#ifdef CONFIG_SPI_0_NRF_SPIM
|
||||
#define NRFX_SPIM0_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIM1_ENABLED - Enable SPIM1 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIM1_ENABLED
|
||||
#define NRFX_SPIM1_ENABLED 0
|
||||
#ifdef CONFIG_SPI_1_NRF_SPIM
|
||||
#define NRFX_SPIM1_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIM2_ENABLED - Enable SPIM2 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIM2_ENABLED
|
||||
#define NRFX_SPIM2_ENABLED 0
|
||||
#ifdef CONFIG_SPI_2_NRF_SPIM
|
||||
#define NRFX_SPIM2_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <o> NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration.
|
||||
|
|
@ -1723,28 +1723,28 @@
|
|||
|
||||
// <e> NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
|
||||
//==========================================================
|
||||
#ifndef NRFX_SPIS_ENABLED
|
||||
#define NRFX_SPIS_ENABLED 0
|
||||
#ifdef CONFIG_NRFX_SPIS
|
||||
#define NRFX_SPIS_ENABLED 1
|
||||
#endif
|
||||
// <q> NRFX_SPIS0_ENABLED - Enable SPIS0 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIS0_ENABLED
|
||||
#define NRFX_SPIS0_ENABLED 0
|
||||
#ifdef CONFIG_SPI_0_NRF_SPIS
|
||||
#define NRFX_SPIS0_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIS1_ENABLED - Enable SPIS1 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIS1_ENABLED
|
||||
#define NRFX_SPIS1_ENABLED 0
|
||||
#ifdef CONFIG_SPI_1_NRF_SPIS
|
||||
#define NRFX_SPIS1_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIS2_ENABLED - Enable SPIS2 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIS2_ENABLED
|
||||
#define NRFX_SPIS2_ENABLED 0
|
||||
#ifdef CONFIG_SPI_2_NRF_SPIS
|
||||
#define NRFX_SPIS2_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <o> NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
|
||||
|
|
@ -1845,28 +1845,28 @@
|
|||
|
||||
// <e> NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
|
||||
//==========================================================
|
||||
#ifndef NRFX_SPI_ENABLED
|
||||
#define NRFX_SPI_ENABLED 0
|
||||
#ifdef CONFIG_NRFX_SPI
|
||||
#define NRFX_SPI_ENABLED 1
|
||||
#endif
|
||||
// <q> NRFX_SPI0_ENABLED - Enable SPI0 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPI0_ENABLED
|
||||
#define NRFX_SPI0_ENABLED 0
|
||||
#ifdef CONFIG_SPI_0_NRF_SPI
|
||||
#define NRFX_SPI0_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPI1_ENABLED - Enable SPI1 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPI1_ENABLED
|
||||
#define NRFX_SPI1_ENABLED 0
|
||||
#ifdef CONFIG_SPI_1_NRF_SPI
|
||||
#define NRFX_SPI1_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPI2_ENABLED - Enable SPI2 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPI2_ENABLED
|
||||
#define NRFX_SPI2_ENABLED 0
|
||||
#ifdef CONFIG_SPI_2_NRF_SPI
|
||||
#define NRFX_SPI2_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <o> NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration.
|
||||
|
|
|
|||
|
|
@ -1712,35 +1712,35 @@
|
|||
|
||||
// <e> NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
|
||||
//==========================================================
|
||||
#ifndef NRFX_SPIM_ENABLED
|
||||
#define NRFX_SPIM_ENABLED 0
|
||||
#ifdef CONFIG_NRFX_SPIM
|
||||
#define NRFX_SPIM_ENABLED 1
|
||||
#endif
|
||||
// <q> NRFX_SPIM0_ENABLED - Enable SPIM0 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIM0_ENABLED
|
||||
#define NRFX_SPIM0_ENABLED 0
|
||||
#ifdef CONFIG_SPI_0_NRF_SPIM
|
||||
#define NRFX_SPIM0_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIM1_ENABLED - Enable SPIM1 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIM1_ENABLED
|
||||
#define NRFX_SPIM1_ENABLED 0
|
||||
#ifdef CONFIG_SPI_1_NRF_SPIM
|
||||
#define NRFX_SPIM1_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIM2_ENABLED - Enable SPIM2 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIM2_ENABLED
|
||||
#define NRFX_SPIM2_ENABLED 0
|
||||
#ifdef CONFIG_SPI_2_NRF_SPIM
|
||||
#define NRFX_SPIM2_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIM3_ENABLED - Enable SPIM3 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIM3_ENABLED
|
||||
#define NRFX_SPIM3_ENABLED 0
|
||||
#ifdef CONFIG_SPI_3_NRF_SPIM
|
||||
#define NRFX_SPIM3_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features
|
||||
|
|
@ -1840,28 +1840,28 @@
|
|||
|
||||
// <e> NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
|
||||
//==========================================================
|
||||
#ifndef NRFX_SPIS_ENABLED
|
||||
#define NRFX_SPIS_ENABLED 0
|
||||
#ifdef CONFIG_NRFX_SPIS
|
||||
#define NRFX_SPIS_ENABLED 1
|
||||
#endif
|
||||
// <q> NRFX_SPIS0_ENABLED - Enable SPIS0 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIS0_ENABLED
|
||||
#define NRFX_SPIS0_ENABLED 0
|
||||
#ifdef CONFIG_SPI_0_NRF_SPIS
|
||||
#define NRFX_SPIS0_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIS1_ENABLED - Enable SPIS1 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIS1_ENABLED
|
||||
#define NRFX_SPIS1_ENABLED 0
|
||||
#ifdef CONFIG_SPI_1_NRF_SPIS
|
||||
#define NRFX_SPIS1_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPIS2_ENABLED - Enable SPIS2 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPIS2_ENABLED
|
||||
#define NRFX_SPIS2_ENABLED 0
|
||||
#ifdef CONFIG_SPI_2_NRF_SPIS
|
||||
#define NRFX_SPIS2_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <o> NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
|
||||
|
|
@ -1948,28 +1948,28 @@
|
|||
|
||||
// <e> NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
|
||||
//==========================================================
|
||||
#ifndef NRFX_SPI_ENABLED
|
||||
#define NRFX_SPI_ENABLED 0
|
||||
#ifdef CONFIG_NRFX_SPI
|
||||
#define NRFX_SPI_ENABLED 1
|
||||
#endif
|
||||
// <q> NRFX_SPI0_ENABLED - Enable SPI0 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPI0_ENABLED
|
||||
#define NRFX_SPI0_ENABLED 0
|
||||
#ifdef CONFIG_SPI_0_NRF_SPI
|
||||
#define NRFX_SPI0_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPI1_ENABLED - Enable SPI1 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPI1_ENABLED
|
||||
#define NRFX_SPI1_ENABLED 0
|
||||
#ifdef CONFIG_SPI_1_NRF_SPI
|
||||
#define NRFX_SPI1_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <q> NRFX_SPI2_ENABLED - Enable SPI2 instance
|
||||
|
||||
|
||||
#ifndef NRFX_SPI2_ENABLED
|
||||
#define NRFX_SPI2_ENABLED 0
|
||||
#ifdef CONFIG_SPI_2_NRF_SPI
|
||||
#define NRFX_SPI2_ENABLED 1
|
||||
#endif
|
||||
|
||||
// <o> NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue