boards: arm: mps2: Add support for mps2/an383
Added new mps2 board an383 to enable testing with ARM FVP. Qualifier to build/run is mps2/an383 Signed-off-by: Samuel Chee <samche01@arm.com>
This commit is contained in:
Samuel Chee
Benjamin Cabé
parent
8373db572f
commit
8d6d4de79d
21 changed files with 662 additions and 279 deletions
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@ -1,6 +1,6 @@
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# Copyright (c) 2017 Linaro Limited
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# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MPS2
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select QEMU_TARGET
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select HAS_COVERAGE_SUPPORT
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select QEMU_TARGET if BOARD_MPS2_AN385 || BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1
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@ -1,7 +1,8 @@
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# Copyright (c) 2017 Linaro Limited
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# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_MPS2_AN385
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if BOARD_MPS2_AN385 || BOARD_MPS2_AN383
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if SERIAL
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@ -1,7 +1,9 @@
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# Copyright (c) 2017 Linaro Limited
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# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MPS2
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select SOC_MPS2_AN383 if BOARD_MPS2_AN383
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select SOC_MPS2_AN385 if BOARD_MPS2_AN385
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select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0
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select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0_NS
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@ -1,7 +1,8 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
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set(SUPPORTED_EMU_PLATFORMS qemu)
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if(CONFIG_BOARD_MPS2_AN385)
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set(QEMU_CPU_TYPE_${ARCH} cortex-m3)
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set(QEMU_FLAGS_${ARCH}
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@ -10,6 +11,14 @@ if(CONFIG_BOARD_MPS2_AN385)
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-nographic
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-vga none
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)
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elseif(CONFIG_BOARD_MPS2_AN383)
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set(SUPPORTED_EMU_PLATFORMS armfvp)
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set(ARMFVP_BIN_NAME FVP_MPS2_Cortex-M0plus)
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set(ARMFVP_FLAGS
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-C armcortexm0plusct.NUM_MPU_REGION=8
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-C armcortexm0plusct.USER=1
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-C armcortexm0plusct.VTOR=1
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)
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elseif(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1)
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set(QEMU_CPU_TYPE_${ARCH} cortex-m33)
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set(QEMU_FLAGS_${ARCH}
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@ -19,11 +28,7 @@ elseif(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG
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-m 16
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-vga none
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)
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endif()
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board_set_debugger_ifnset(qemu)
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if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1)
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# To enable a host tty switch between serial and pty
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# -chardev serial,path=/dev/ttyS0,id=hostS0
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# pty is not available on Windows.
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@ -44,3 +49,18 @@ if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOA
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list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}")
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endif()
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endif()
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board_set_debugger_ifnset(qemu)
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set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
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-C fvp_mps2.telnetterminal0.start_telnet=0
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-C fvp_mps2.telnetterminal1.start_telnet=0
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-C fvp_mps2.telnetterminal2.start_telnet=0
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-C fvp_mps2.UART0.out_file=-
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-C fvp_mps2.UART0.unbuffered_output=1
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-C fvp_mps2.UART1.out_file=-
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-C fvp_mps2.UART1.unbuffered_output=1
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-C fvp_mps2.UART2.out_file=-
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-C fvp_mps2.UART2.unbuffered_output=1
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-C fvp_mps2.mps2_visualisation.disable-visualisation=1
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)
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@ -3,6 +3,7 @@ board:
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full_name: V2M MPS2
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vendor: arm
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socs:
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- name: an383
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- name: an385
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- name: an521
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variants:
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Before Width: | Height: | Size: 62 KiB After Width: | Height: | Size: 62 KiB |
Binary file not shown.
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Before Width: | Height: | Size: 34 KiB |
271
boards/arm/mps2/doc/mps2_an383.rst
Normal file
271
boards/arm/mps2/doc/mps2_an383.rst
Normal file
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.. _mps2_an383_board:
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ARM V2M MPS2 AN383
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##################
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Overview
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********
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The ``mps2/an383`` board target is used by Zephyr applications that run on
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the V2M MPS2 board. It provides support for the ARM Cortex-M0+ (AN383) CPU and
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the following devices:
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- Nested Vectored Interrupt Controller (NVIC)
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- System Tick System Clock (SYSTICK)
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- Cortex-M System Design Kit UART
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.. image:: img/mps2.jpg
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:align: center
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:alt: ARM V2M MPS2
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In addition to enabling actual hardware usage, this board target can
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also use `FVP`_. to emulate the AN383 platform running on the MPS2+.
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More information about the board can be found at the `V2M MPS2 Website`_.
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The Application Note AN383 can be found at `Application Note AN383`_.
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.. note::
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This board target makes no claims about its suitability for use
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with actual MPS2 hardware systems using AN383, or any other hardware
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system. It has been tested on FVP.
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Hardware
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********
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ARM V2M MPS2 AN383 provides the following hardware components:
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- ARM Cortex-M0+
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- ARM IoT Subsystem for Cortex-M
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- Form factor: 140x120cm
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- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM
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- Video: QSVGA touch screen panel, 4bit RGB VGA connector
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- Audio: Audio Codec
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- Debug:
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- ARM JTAG20 connector
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- ARM parallel trace connector (MICTOR38)
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- 20 pin Cortex debug connector
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- 10 pin Cortex debug connector
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- ILA connector for FPGA debug
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- Expansion
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- GPIO
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- SPI
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.. note::
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4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM
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(in ZBTSRAM 2 & 3, starting at address 0x20000000) are available.
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Supported Features
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==================
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The ``mps2/an383`` board target supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| WATCHDOG | on-chip | watchdog |
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+-----------+------------+-------------------------------------+
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| TIMER | on-chip | counter |
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+-----------+------------+-------------------------------------+
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| DUALTIMER | on-chip | counter |
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+-----------+------------+-------------------------------------+
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Other hardware features are not currently supported by the port.
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See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware
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features.
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The default configuration can be found in
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:zephyr_file:`boards/arm/mps2/mps2_an383_defconfig`
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Interrupt Controller
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====================
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MPS2 is a Cortex-M0+ based SoC and has 6 fixed exceptions and 32 IRQs.
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A Cortex-M0+ board uses vectored exceptions. This means each exception
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calls a handler directly from the vector table.
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Handlers are provided for exceptions 1-3, 11, and 14-15. The table here
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MPS2 is a Cortex-M0+ based SoC and has 15 fixed exceptions and 45 IRQs.
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+------+------------+----------------+--------------------------+
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| Exc# | Name | Remarks | Used by Zephyr Kernel |
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+======+============+================+==========================+
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| 1 | Reset | | system initialization |
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+------+------------+----------------+--------------------------+
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| 2 | NMI | | system fatal error |
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+------+------------+----------------+--------------------------+
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| 3 | Hard fault | | system fatal error |
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+------+------------+----------------+--------------------------+
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| 11 | SVC | | system calls, kernel |
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| | | | run-time exceptions, |
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| | | | and IRQ offloading |
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+------+------------+----------------+--------------------------+
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| 14 | PendSV | | context switch |
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+------+------------+----------------+--------------------------+
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| 15 | SYSTICK | optional | system clock |
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+------+------------+----------------+--------------------------+
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Pin Mapping
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===========
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The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible
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for pin muxing, input/output, pull-up, etc.
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All GPIO controller pins are exposed via the following sequence of pin numbers:
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- Pins 0 - 15 are for GPIO 0
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- Pins 16 - 31 are for GPIO 1
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- Pins 32 - 47 are for GPIO 2
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- Pins 48 - 51 are for GPIO 3
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Mapping from the ARM MPS2 Board pins to GPIO controllers:
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.. rst-class:: rst-columns
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- D0 : EXT_0
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- D1 : EXT_4
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- D2 : EXT_2
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- D3 : EXT_3
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- D4 : EXT_1
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- D5 : EXT_6
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- D6 : EXT_7
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- D7 : EXT_8
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- D8 : EXT_9
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- D9 : EXT_10
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- D10 : EXT_12
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- D11 : EXT_13
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- D12 : EXT_14
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- D13 : EXT_11
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- D14 : EXT_15
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- D15 : EXT_5
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- D16 : EXT_16
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- D17 : EXT_17
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- D18 : EXT_18
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- D19 : EXT_19
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- D20 : EXT_20
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- D21 : EXT_21
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- D22 : EXT_22
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- D23 : EXT_23
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- D24 : EXT_24
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- D25 : EXT_25
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- D26 : EXT_26
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- D27 : EXT_30
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- D28 : EXT_28
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- D29 : EXT_29
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- D30 : EXT_27
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- D31 : EXT_32
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- D32 : EXT_33
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- D33 : EXT_34
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- D34 : EXT_35
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- D35 : EXT_36
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- D36 : EXT_38
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- D37 : EXT_39
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- D38 : EXT_40
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- D39 : EXT_44
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- D40 : EXT_41
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- D41 : EXT_31
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- D42 : EXT_37
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- D43 : EXT_42
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- D44 : EXT_43
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- D45 : EXT_45
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- D46 : EXT_46
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- D47 : EXT_47
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- D48 : EXT_48
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- D49 : EXT_49
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- D50 : EXT_50
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- D51 : EXT_51
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Peripheral Mapping:
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.. rst-class:: rst-columns
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- UART_3_RX : D0
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- UART_3_TX : D1
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- SPI_3_CS : D10
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- SPI_3_MOSI : D11
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- SPI_3_MISO : D12
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- SPI_3_SCLK : D13
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- I2C_3_SDA : D14
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- I2C_3_SCL : D15
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- UART_4_RX : D26
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- UART_4_TX : D30
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- SPI_4_CS : D36
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- SPI_4_MOSI : D37
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- SPI_4_MISO : D38
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- SPI_4_SCK : D39
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- I2C_4_SDA : D40
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- I2C_4_SCL : D41
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For more details please refer to `MPS2 Technical Reference Manual (TRM)`_.
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System Clock
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============
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The V2M MPS2 main clock is 24 MHz.
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Serial Port
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===========
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The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for
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RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by
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default, is utilizing UART0.
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Programming and Debugging
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*************************
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Flashing
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========
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V2M MPS2 provides:
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- A USB connection to the host computer, which exposes a Mass Storage and an
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USB Serial Port.
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- A Serial Flash device, which implements the USB flash disk file storage.
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- A physical UART connection which is relayed over interface USB Serial port.
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Flashing an application to V2M MPS2
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-----------------------------------
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Here is an example for the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: mps2/an383
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:goals: build
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Connect the V2M MPS2 to your host computer using the USB port and you should
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see a USB connection which exposes a Mass Storage and a USB Serial Port.
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Copy the generated zephyr.bin in the exposed drive.
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Reset the board and you should be able to see on the corresponding Serial Port
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the following message:
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.. code-block:: console
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Hello World! arm
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.. _V2M MPS2 Website:
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https://developer.mbed.org/platforms/ARM-MPS2/
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.. _MPS2 Technical Reference Manual (TRM):
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http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf
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.. _Application Note AN383:
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https://documentation-service.arm.com/static/5ed1051dca06a95ce53f88a1
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.. _FVP:
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https://developer.arm.com/downloads/view/FMFVP
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@ -1,7 +1,7 @@
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.. _mps2_an385_board:
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ARM V2M MPS2
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############
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ARM V2M MPS2 AN385
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##################
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Overview
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********
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@ -14,7 +14,7 @@ the following devices:
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- System Tick System Clock (SYSTICK)
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- Cortex-M System Design Kit UART
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.. image:: img/mps2_an385.jpg
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.. image:: img/mps2.jpg
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:align: center
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:alt: ARM V2M MPS2
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@ -15,7 +15,7 @@ CPU and the following devices:
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- Cortex-M System Design Kit GPIO
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- Cortex-M System Design Kit UART
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.. image:: img/mps2_an521.jpg
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.. image:: img/mps2.jpg
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:align: center
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:alt: ARM MPS2+ AN521
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30
boards/arm/mps2/mps2_an383.dts
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30
boards/arm/mps2/mps2_an383.dts
Normal file
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@ -0,0 +1,30 @@
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/*
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* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm/armv6-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include "mps2_base.dtsi"
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/* FVP does not support uart3 and uart4 */
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/* hence we delete them for AN383 in FVP */
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/delete-node/ &uart3;
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/delete-node/ &uart4;
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0+";
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reg = <0>;
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};
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};
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};
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19
boards/arm/mps2/mps2_an383.yaml
Normal file
19
boards/arm/mps2/mps2_an383.yaml
Normal file
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@ -0,0 +1,19 @@
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identifier: mps2/an383
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name: ARM V2M MPS2-an383
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type: mcu
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arch: arm
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simulation:
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- name: armfvp
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exec: FVP_MPS2_Cortex-M0plus
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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supported:
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- counter
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- netif:serial-net
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- gpio
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- watchdog
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testing:
|
||||
default: true
|
||||
vendor: arm
|
||||
20
boards/arm/mps2/mps2_an383_defconfig
Normal file
20
boards/arm/mps2/mps2_an383_defconfig
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
#
|
||||
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
CONFIG_RUNTIME_NMI=y
|
||||
|
||||
# GPIOs
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Serial
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_SERIAL=y
|
||||
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# 0x0 is a valid address, we cannot prevent access to that area
|
||||
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
|
||||
|
|
@ -1,58 +1,17 @@
|
|||
/* SPDX-License-Identifier: Apache-2.0 */
|
||||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include <zephyr/dt-bindings/i2c/i2c.h>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
#include "mps2_base.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "arm,mps2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
led0 = &led_0;
|
||||
led1 = &led_1;
|
||||
sw0 = &user_button_0;
|
||||
sw1 = &user_button_1;
|
||||
watchdog0 = &wdog0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,uart-pipe = &uart1;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,flash = &flash0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led_0: led_0 {
|
||||
gpios = <&gpio_led0 0>;
|
||||
label = "USERLED0";
|
||||
};
|
||||
led_1: led_1 {
|
||||
gpios = <&gpio_led0 1>;
|
||||
label = "USERLED1";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
user_button_0: button_0 {
|
||||
label = "USERPB0";
|
||||
gpios = <&gpio_button 0>;
|
||||
zephyr,code = <INPUT_KEY_0>;
|
||||
};
|
||||
user_button_1: button_1 {
|
||||
label = "USERPB1";
|
||||
gpios = <&gpio_button 1>;
|
||||
zephyr,code = <INPUT_KEY_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -62,223 +21,4 @@
|
|||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x20000000 0x400000>;
|
||||
};
|
||||
|
||||
flash0: flash@0 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0 0x400000>;
|
||||
};
|
||||
|
||||
sim_flash_controller: sim_flash_controller {
|
||||
compatible = "zephyr,sim-flash";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
erase-value = <0x00>;
|
||||
|
||||
flash_sim0: flash_sim@0 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x00000000 0x8000>;
|
||||
|
||||
erase-block-size = <1024>;
|
||||
write-block-size = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
storage_partition: partition@0 {
|
||||
label = "storage_partition";
|
||||
reg = <0x00000000 0x8000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sysclk: system-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
timer0: timer@40000000 {
|
||||
compatible = "arm,cmsdk-timer";
|
||||
reg = <0x40000000 0x1000>;
|
||||
interrupts = <8 3>;
|
||||
};
|
||||
|
||||
timer1: timer@40001000 {
|
||||
compatible = "arm,cmsdk-timer";
|
||||
reg = <0x40001000 0x1000>;
|
||||
interrupts = <9 3>;
|
||||
};
|
||||
|
||||
dtimer0: dtimer@40002000 {
|
||||
compatible = "arm,cmsdk-dtimer";
|
||||
reg = <0x40002000 0x1000>;
|
||||
interrupts = <10 3>;
|
||||
};
|
||||
|
||||
uart0: uart@40004000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40004000 0x1000>;
|
||||
interrupts = <1 3 0 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
uart1: uart@40005000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40005000 0x1000>;
|
||||
interrupts = <3 3 2 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
uart2: uart@40006000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40006000 0x1000>;
|
||||
interrupts = <5 3 4 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
uart3: uart@40007000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40007000 0x1000>;
|
||||
interrupts = <19 3 18 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
wdog0: wdog@40008000 {
|
||||
compatible = "arm,cmsdk-watchdog";
|
||||
clocks = <&sysclk>;
|
||||
reg = <0x40008000 0x1000>;
|
||||
};
|
||||
|
||||
uart4: uart@40009000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40009000 0x1000>;
|
||||
interrupts = <21 3 20 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
gpio0: gpio@40010000 {
|
||||
compatible = "arm,cmsdk-gpio";
|
||||
reg = <0x40010000 0x1000>;
|
||||
interrupts = <6 3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@40011000 {
|
||||
compatible = "arm,cmsdk-gpio";
|
||||
reg = <0x40011000 0x1000>;
|
||||
interrupts = <7 3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@40012000 {
|
||||
compatible = "arm,cmsdk-gpio";
|
||||
reg = <0x40012000 0x1000>;
|
||||
interrupts = <16 3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@40013000 {
|
||||
compatible = "arm,cmsdk-gpio";
|
||||
reg = <0x40013000 0x1000>;
|
||||
interrupts = <17 3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
eth0: eth@40200000 {
|
||||
/* Linux has "smsc,lan9115" */
|
||||
compatible = "smsc,lan9220";
|
||||
/* Such a big size from memory map in AN385 */
|
||||
/* Actual reg range is ~0x200 */
|
||||
reg = <0x40200000 0x100000>;
|
||||
interrupts = <13 3>;
|
||||
};
|
||||
|
||||
i2c_touch: i2c@40022000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40022000 0x1000>;
|
||||
};
|
||||
|
||||
i2c_audio_conf: i2c@40023000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40023000 0x1000>;
|
||||
};
|
||||
|
||||
i2c_shield0: i2c@40029000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40029000 0x1000>;
|
||||
};
|
||||
|
||||
i2c_shield1: i2c@4002a000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4002a000 0x1000>;
|
||||
};
|
||||
|
||||
gpio_led0: mps2_fpgaio@40028000 {
|
||||
compatible = "arm,mps2-fpgaio-gpio";
|
||||
|
||||
reg = <0x40028000 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
ngpios = <2>;
|
||||
};
|
||||
|
||||
gpio_button: mps2_fpgaio@40028008 {
|
||||
compatible = "arm,mps2-fpgaio-gpio";
|
||||
|
||||
reg = <0x40028008 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
ngpios = <2>;
|
||||
};
|
||||
|
||||
gpio_misc: mps2_fpgaio@4002804c {
|
||||
compatible = "arm,mps2-fpgaio-gpio";
|
||||
|
||||
reg = <0x4002804c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
ngpios = <10>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
|
|
|
|||
265
boards/arm/mps2/mps2_base.dtsi
Normal file
265
boards/arm/mps2/mps2_base.dtsi
Normal file
|
|
@ -0,0 +1,265 @@
|
|||
/* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> */
|
||||
/* SPDX-License-Identifier: Apache-2.0 */
|
||||
|
||||
/ {
|
||||
compatible = "arm,mps2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
led0 = &led_0;
|
||||
led1 = &led_1;
|
||||
sw0 = &user_button_0;
|
||||
sw1 = &user_button_1;
|
||||
watchdog0 = &wdog0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,uart-pipe = &uart1;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,flash = &flash0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led_0: led_0 {
|
||||
gpios = <&gpio_led0 0>;
|
||||
label = "USERLED0";
|
||||
};
|
||||
|
||||
led_1: led_1 {
|
||||
gpios = <&gpio_led0 1>;
|
||||
label = "USERLED1";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
user_button_0: button_0 {
|
||||
label = "USERPB0";
|
||||
gpios = <&gpio_button 0>;
|
||||
zephyr,code = <INPUT_KEY_0>;
|
||||
};
|
||||
|
||||
user_button_1: button_1 {
|
||||
label = "USERPB1";
|
||||
gpios = <&gpio_button 1>;
|
||||
zephyr,code = <INPUT_KEY_1>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x20000000 0x400000>;
|
||||
};
|
||||
|
||||
flash0: flash@0 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0 0x400000>;
|
||||
};
|
||||
|
||||
sim_flash_controller: sim_flash_controller {
|
||||
compatible = "zephyr,sim-flash";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
erase-value = <0x00>;
|
||||
|
||||
flash_sim0: flash_sim@0 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x00000000 0x8000>;
|
||||
erase-block-size = <1024>;
|
||||
write-block-size = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
storage_partition: partition@0 {
|
||||
label = "storage_partition";
|
||||
reg = <0x00000000 0x8000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sysclk: system-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
timer0: timer@40000000 {
|
||||
compatible = "arm,cmsdk-timer";
|
||||
reg = <0x40000000 0x1000>;
|
||||
interrupts = <8 3>;
|
||||
};
|
||||
|
||||
timer1: timer@40001000 {
|
||||
compatible = "arm,cmsdk-timer";
|
||||
reg = <0x40001000 0x1000>;
|
||||
interrupts = <9 3>;
|
||||
};
|
||||
|
||||
dtimer0: dtimer@40002000 {
|
||||
compatible = "arm,cmsdk-dtimer";
|
||||
reg = <0x40002000 0x1000>;
|
||||
interrupts = <10 3>;
|
||||
};
|
||||
|
||||
uart0: uart@40004000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40004000 0x1000>;
|
||||
interrupts = <1 3 0 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
uart1: uart@40005000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40005000 0x1000>;
|
||||
interrupts = <3 3 2 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
uart2: uart@40006000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40006000 0x1000>;
|
||||
interrupts = <5 3 4 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
uart3: uart@40007000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40007000 0x1000>;
|
||||
interrupts = <19 3 18 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
wdog0: wdog@40008000 {
|
||||
compatible = "arm,cmsdk-watchdog";
|
||||
clocks = <&sysclk>;
|
||||
reg = <0x40008000 0x1000>;
|
||||
};
|
||||
|
||||
uart4: uart@40009000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40009000 0x1000>;
|
||||
interrupts = <21 3 20 3>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&sysclk>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
gpio0: gpio@40010000 {
|
||||
compatible = "arm,cmsdk-gpio";
|
||||
reg = <0x40010000 0x1000>;
|
||||
interrupts = <6 3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@40011000 {
|
||||
compatible = "arm,cmsdk-gpio";
|
||||
reg = <0x40011000 0x1000>;
|
||||
interrupts = <7 3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@40012000 {
|
||||
compatible = "arm,cmsdk-gpio";
|
||||
reg = <0x40012000 0x1000>;
|
||||
interrupts = <16 3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@40013000 {
|
||||
compatible = "arm,cmsdk-gpio";
|
||||
reg = <0x40013000 0x1000>;
|
||||
interrupts = <17 3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
eth0: eth@40200000 {
|
||||
/* Linux has "smsc,lan9115" */
|
||||
compatible = "smsc,lan9220";
|
||||
/* Such a big size from memory map in AN385 */
|
||||
/* Actual reg range is ~0x200 */
|
||||
reg = <0x40200000 0x100000>;
|
||||
interrupts = <13 3>;
|
||||
};
|
||||
|
||||
i2c_touch: i2c@40022000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40022000 0x1000>;
|
||||
};
|
||||
|
||||
i2c_audio_conf: i2c@40023000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40023000 0x1000>;
|
||||
};
|
||||
|
||||
i2c_shield0: i2c@40029000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40029000 0x1000>;
|
||||
};
|
||||
|
||||
i2c_shield1: i2c@4002a000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4002a000 0x1000>;
|
||||
};
|
||||
|
||||
gpio_led0: mps2_fpgaio@40028000 {
|
||||
compatible = "arm,mps2-fpgaio-gpio";
|
||||
reg = <0x40028000 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
ngpios = <2>;
|
||||
};
|
||||
|
||||
gpio_button: mps2_fpgaio@40028008 {
|
||||
compatible = "arm,mps2-fpgaio-gpio";
|
||||
reg = <0x40028008 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
ngpios = <2>;
|
||||
};
|
||||
|
||||
gpio_misc: mps2_fpgaio@4002804c {
|
||||
compatible = "arm,mps2-fpgaio-gpio";
|
||||
reg = <0x4002804c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
ngpios = <10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
|
|
@ -147,6 +147,13 @@ static int gpio_mmio32_port_toggle_bits(const struct device *dev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int gpio_mmio_pin_interrupt_configure(const struct device *port,
|
||||
gpio_pin_t pin,
|
||||
enum gpio_int_mode, enum gpio_int_trig)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
DEVICE_API(gpio, gpio_mmio32_api) = {
|
||||
.pin_configure = gpio_mmio32_config,
|
||||
.port_get_raw = gpio_mmio32_port_get_raw,
|
||||
|
|
@ -154,6 +161,7 @@ DEVICE_API(gpio, gpio_mmio32_api) = {
|
|||
.port_set_bits_raw = gpio_mmio32_port_set_bits_raw,
|
||||
.port_clear_bits_raw = gpio_mmio32_port_clear_bits_raw,
|
||||
.port_toggle_bits = gpio_mmio32_port_toggle_bits,
|
||||
.pin_interrupt_configure = gpio_mmio_pin_interrupt_configure,
|
||||
};
|
||||
|
||||
int gpio_mmio32_init(const struct device *dev)
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
# Copyright (c) 2024, Nordic Semiconductor ASA
|
||||
|
||||
if(CONFIG_BOARD_MPS2_AN521_CPUTEST)
|
||||
set(SUPPORTED_EMU_PLATFORMS qemu)
|
||||
set(QEMU_CPU_TYPE_${ARCH} cortex-m33)
|
||||
set(QEMU_FLAGS_${ARCH}
|
||||
-cpu ${QEMU_CPU_TYPE_${ARCH}}
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ tests:
|
|||
platform_exclude:
|
||||
- mps2/an385
|
||||
- mps2/an521/cpu0
|
||||
- mps2/an383
|
||||
- neorv32
|
||||
drivers.gpio.1pin.aw9523b:
|
||||
tags:
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ tests:
|
|||
- s32z2xxdc2/s32z270/rtu1
|
||||
- s32z2xxdc2@D/s32z270/rtu0
|
||||
- s32z2xxdc2@D/s32z270/rtu1
|
||||
- mps2/an383
|
||||
drivers.watchdog.stm32wwdg:
|
||||
filter: dt_compat_enabled("st,stm32-window-watchdog") or dt_compat_enabled("st,stm32-watchdog")
|
||||
extra_args: DTC_OVERLAY_FILE="boards/stm32_wwdg.overlay"
|
||||
|
|
|
|||
|
|
@ -11,7 +11,9 @@ common:
|
|||
# FIXME: This test fails very frequently on mps2/an385 due to the system
|
||||
# timer stability issues, so keep it disabled until the root cause
|
||||
# is fixed (GitHub issue zephyrproject-rtos/zephyr#48608).
|
||||
platform_exclude: mps2/an385
|
||||
platform_exclude:
|
||||
- mps2/an385
|
||||
- mps2/an383
|
||||
tests:
|
||||
net.socket.tcp:
|
||||
extra_configs:
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ common:
|
|||
- s32z2xxdc2/s32z270/rtu1 # See commit 18a0660
|
||||
# platforms that are always skipped by the runtime filter
|
||||
- qemu_cortex_m0
|
||||
- mps2/an383
|
||||
- qemu_xtensa/dc233c/mmu
|
||||
integration_platforms:
|
||||
- qemu_cortex_a9 # ARM Cortex-A9 (ARMv7-A ISA)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue