There are multiple issues in this driver:
1. gpio_pca_series_part_cfg_pca6416 is not using correct macros
2. gpio_pca_series_interrupt_handler_standard not updating input when
no interrupt configured
Fixing these issues.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Some variants of the PCA953x family support pull-up / pull-down
resistors through registers 0x43 and 0x44 (mostly the TCAL9538 variant).
We already support input latching and interrupt masking (which is also
only present on a few variants), so let's also add support for pull-up
and pull-down resistors.
The feature can be enabled with the has-pud property in the device tree.
Signed-off-by: Marco Widmer <marco.widmer@bytesatwork.ch>
For all STM32 drivers and SoC, replace the READ_REG macro and the
LL_xxx_ReadReg functions (defined in the STM32 HAL) by
stm32_reg_read defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the WRITE_REG macro and the
LL_xxx_WriteReg functions (defined in the STM32 HAL) by
stm32_reg_write defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The condition for setting the GPOMD bit when `port0_push_pull`
is enabled was reversed.
Fix this problem.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The reset GPIO for the SN74HC595 driver was not working anymore since
c407fbc. That commit made it optional among other changes but
accidently removed the s from reset_gpios property name causing the
driver not being able to retrieve the specified reset-gpios property
from the devicetree anymore. Add the missing s back to fix this.
Signed-off-by: Michael Klammt <michael.klammt@automatic-research.de>
When GPIO works with IOPCTL, the PIO instance offset in IOPCTL
can't be calculated easily. It should be recorded in DTS based on
SOC integration.
When IOPCTL is used, add PIO reigster address in DTS, gpio_mcux
driver will configure the PIO register based on this address.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Drop usage of `pcfg` and `pdata` in favor of unified `cfg`
for common configuration and `port_cfg`, `port_data` for
port-specific configurations.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Add the port_count field to the configuration structure
and allocate different sizes for the ports array based
on whether the node is HP or ULP.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Replace the pad group integration with directly setting/clearing
pin retention for output pins if required, since the pad group
integration is redundant if the quirky cross domain feature is
managed by the application.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Kconfig symbols for selecting HAL content should be part of the
HAL module integration, not defined in the SoC tree.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Enable support for latest GINF method which requires 3 paramters
for each GPIO group and enables gpio support for intel_ptl_h
platform.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Add basic support for the Aesc Silicon GPIO controller.
This IP core has internal tri-states and therefore a read,
write and direction registers. Additionally, it has advanced
monitoring capabilities for interrupt generation; low or
high leve and rising or falling edge.
Interrupt support will be added later when ElemRV supports
interrupt in Zephyr.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add condition to check whether the pin is set as output before
reading the output high or low for gpio driver of Renesas RZ
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
support gpio wake up function.
change init stage from POST_KERNEL to PRE_KERNEL_1
because uart wrap init need to use the gpio functions.
Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
This macro doesn't accept a delay parameter anymore (well, it does, but
it's deprecated and will trigger build warnings). Just remove it from the
places that were still passing it.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
ASAN reports error with native_sim after "gpio info <TAB>":
runtime error: index 1 out of bounds for type 'gpio_ctrl [1]'
So, although the dev pointer was not used, don't even read it
from out-of-bounds of gpio_list.
Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
On certain platforms I2C is not enabled by default, causing build error.
Change pca_series driver to select I2C.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The reset function is originally designed to have no return value. If
the GPIO toggle fails, there's no indication for failure until I2C
transaction fails. Account for this by adding return value to the reset
function.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
add support for pca9538, pcal9539.
Add support for pcal6408 and pcal6416, which is originally supported
by pcal64xxa driver. These device has the same register layout as
pcal9538 and pcal9539 respectively, which means they can be seamlessly
supported by pca_series driver.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
This commit updates the function to only set output-related flags
(GPIO_OUTPUT_INIT_HIGH, GPIO_OUTPUT_INIT_LOW) when the pin
is actually configured as output. For input pins, only GPIO_INPUT and
other relevant flags are set.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
The SIUL2 external interrupt driver is a native implementation usable
across all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow
clean reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The SIUL2 GPIO driver is a native implementation usable across all
NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Enable the pin configuration as single-ended pull-up output, allowing for
a currentless, signal-only output.
Signed-off-by: Paulo Santos <pauloroberto.santos@edge.ufal.br>
The fast wake feature in the MSPM0 GPIO peripheral allows the GPIO module
to stay in a low-power state and detect interrupt events on the device pins
without requiring a high-speed clock. This allows the device to support
fast wakeup from low-power modes, such as STOP and STANDBY, on any GPIO
pin.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
EM4 wakeup interrupts are dedicated interrupts tied to specific
pins that enable wakeup from EM4 through reset. Add support
for using these interrupts instead of the regular interrupts when
the GPIO_INT_TRIG_WAKE flag is set.
Since it's not possible to tell what pin is associated with what
EM4WU interrupt at runtime, the driver must store a mapping table
sourced from device tree.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
GPIO interrupts do not work on MCXA, MCXA has ICR register but feature
FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT value is 0, can't only use
this feature to support ICR. So adjust feature judgment.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
There will be an compilation error if there is no interrupt GPIO defined
in the device tree file, as parts of the config and data structs
have #if that depends on the presence of interrupt GPIO.
Use the same #if constructs also on the functions that use those
structs.
Signed-off-by: Jonas Berg <jonas.s.t.berg@gmail.com>
The current driver has a few limitations:
1. The `ngpios` DT property is fixed at eight.
Since the SN74HC595 and kin are designed to be
easily daisychain-able, the upper bound on `ngpios`
should be limited only by the maximum number of pins
that Zephyr supports per GPIO port, which is 32.
2. In the case of having no control over the shift register's
reset input, the device tree node should accept a default
value to shift into the register(s) during init.
3. There seems to be an assumption that the serial clock
and load clock are tied together. While this is often the
case, the device tree node should be more flexible in
allowing the specification of a separate load clock GPIO pin.
4. The device tree node should also be able to accept a GPIO pin
to drive the enable input pin of the shift register(s).
This commit addresses all of these issues.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Remove the configs that are not actually used for anything anymore or
never were, or that are redundant with other configs, and don't have any
code changes outside of Kconfig to remove.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
