Remove dead clock gate code and associated PM code as the platforms
that used the clock gate code are no longer supported in Zephyr.
Signed-off-by: Kumar Gala <galak@kernel.org>
The shared IRQ code has been broken for several releases and no one
seems to have noticed. The platforms that this was used on are not
supported in Zephyr anymore so remove the code.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add gpio_pin_get_config function to gpio_driver_api.
This function is used to read current configuration of pin.
The gpio_pin_get_config checks if driver implements this function and
returns -ENOSYS if it isn't implemented.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Now that we have 8 bits reserved for vendor specific GPIO flags,
introduce a new set of flags for nRF platforms to configure pins drive
mode. These new flags are equivalent to the previous existing ones, but
use a naming scheme the fits better with vendor hardware capabilities.
The table below shows the equivalence between old and new flag
| Old flags | New flags |
|---------------------------|-----------------------|
| `NRF_GPIO_DS_DFLT_LOW` | `NRF_GPIO_DRIVE_S0` |
| `NRF_GPIO_DS_DFLT_HIGH` | `NRF_GPIO_DRIVE_S1` |
| `NRF_GPIO_DS_ALT_LOW` | `NRF_GPIO_DRIVE_H0` |
| `NRF_GPIO_DS_ALT_HIGH` | `NRF_GPIO_DRIVE_H1` |
| `NRF_GPIO_DS_DFLT` | `NRF_GPIO_DRIVE_S0S1` |
| `NRF_GPIO_DS_ALT` | `NRF_GPIO_DRIVE_H0H1` |
| `NRF_GPIO_DS_DFLT_LOW \|` | `NRF_GPIO_DRIVE_S0H1` |
| `NRF_GPIO_DS_ALT_HIGH` | |
| `NRF_GPIO_DS_ALT_LOW \|` | `NRF_GPIO_DRIVE_H0S1` |
| `NRF_GPIO_DS_DFLT_HIGH` | |
Documentation has been written to explain in more detail the meaning of
the flags and how they can be used.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The naming of the custom DS flags is not clear for nRF platforms. This
patch removes all the NRF_GPIO_DS* flags. New flags will be
re-introduced in a follow-up commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In npcx series, not all GPIO pads support Multi-Input Wake-Up Unit
(MIWU) functionality. Hence, this CL adds checking whether GPIO's pad
configuration is valid first before using it.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The TI SimpleLink SDK got updated to version '4.40.04.04' in 'hal_ti'.
This introduced renames of some functions in HAL and has to be reflected
in Zephyr drivers which make use of them.
This renames 'PRCMPowerDomainStatus' to 'PRCMPowerDomainsAllOn' in all
affected 'cc13xx_cc26xx' drivers.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In prepration for configuring I2C/SPI defaults at the board level,
change the DesignWare GPIO driver's clock gate option to depend on clock
control instead of selecting clock control. This breaks a Kconfig
dependency loop when adding the following to a board's
Kconfig.defconfig:
config SPI
default y if SENSOR
There aren't any in-tree users that enable the clock gate option, so
there aren't any places in-tree that now need to enable the clock
control driver. Out-of-tree users that set CONFIG_GPIO_DW_CLOCK_GATE=y
will now also need to set CONFIG_CLOCK_CONTROL=y.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
if ISR is called for an event on pin X but
another event occurs on pin Y in between the call
to GetStatus() and ClrStatus(), pin Y event wil get
cleared without being processed
Signed-off-by: Maxim Adelman <imax@fb.com>
The driver returns -EIO when a pin to be disconnected was not earlier
configured as input or output, what is not in line with the GPIO API.
This commit changes the driver to return 0 in such case.
Also -EIO is incorrectly returned when an interrupt trigger cannot be
configured in the nrfx_gpiote driver. This commit corrects this value
to -EINVAL.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Some services require the ability to query whether a GPIO pin
is configured as an input, output, both, or neither prior to
performing any operations at the service level. This is done
in order to reduce state tracking within the service.
To that end, this change adds
* `gpio_port_get_direction()`
* `gpio_pin_is_input()`, and
* `gpio_pin_is_output()`
Signed-off-by: Christopher Friedt <cfriedt@fb.com>
Stop relying on <soc.h> to access HAL APIs. Use generic, per-API headers
instead. Note that <soc.h> has been left as is for now, since ARM MPU
relies on a fragile chain of includes/type definitions.
This change should improve compilation efficiency, as we no longer pull
APIs that are not needed. A similar approach is followed by STM32
drivers.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit drops the `IRAM_ATTR` macro from the function declarations
because:
1. `IRAM_ATTR` macro makes use of the `__COUNTER__` preprocessor macro,
which increments for every macro invocation and causes the section
specified in the forward declaration to not match that of the
function definition.
2. Section attributes need not be specified for forward declarations.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
All the gpio drivers are based on devicetree and thus we always set
HAS_DTS_GPIO, thus we don't need this Kconfig option anymore. Remove
uses as its safe to assume DTS is supported for GPIO.
Signed-off-by: Kumar Gala <galak@kernel.org>
Remove unconditional write to PCA95xx output registers in setup_pin_dir,
and only write to output registers if selected pin is configured as
an output.
Fixes#45774
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
some iMX RT SOCs have non contiguous sets of gpio pins available, which
caused issues when selecting appropriate pinmux for these parts. Add
workaround code to adjust offset of pinmux settings when configuring
these pins.
Fixes#44391
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Incorrect GPIOTE channel was being freed because the pin number
being used is not the absolute pin but the pin within the port.
Signed-off-by: Wael Barakat <waelsbarakat@gmail.com>
Add pin control support to gpio_imx driver, so that GPIO pin muxes will
be selected when the use configures a pin as GPIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add additional pin controller settings for iMX application core SOCs, as
well as a "fallback" pin control setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
A missing semicolon caused compiler errors when more than one emulated
gpio device was defined in the device tree.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
switch gpio driver to use pio nodes to configure pin control settings,
and stop using pinmux driver within gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Set the PCR[MUX] field to kPORT_MuxAsGpio as part of configuring a GPIO
pin. This removes the need to explicitly call pinmux_pin_set() in board
code.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
add support for setting pinmux when using IOPCTL peripheral, as well as
setting pin configuration properties.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Introduce has-interrupt-mask-reg DTS property for nxp,pca95xx driver.
This additionnal property allow to specify that the gpio expander has an
interrupt mask register that must be configured by the driver.
This allow to use this driver with PCAL95xx.
This fixes issue #44834.
Signed-off-by: Xavier Chapron <xavier.chapron@stimio.fr>
Based on introduction of plain GPIO configurations in STM32 pinctrl
bindings, update STM32 pinctrl/gpio drivers to make this functionality
available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before updating stm32 pinctrl/gpio drivers to support plain GPIO
feature, rework pin configuration functions headers to provide
more clarity on the arguments and the information they convey:
- pin configuration
- pin function
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
