Add NETC block driver, it could do some block memory region MMIO mapping
and also so dome block initialization, moved some netc related
configuration form board_init() to block driver so that it could be reused
between different platforms, although some configuration is different for
different platform, but put all NETC related code in the same driver to
make it easier to be maintained.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Initially phy_link_callback_set got called before iface init got set.
Moving to iface_init, fixes an issue that mac would set interface to up
even though it was down because startup phy down callback didn't got
through.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
remove the use of phy_configure_link() in the ethernet drivers.
The user can now select the default speeds via DT prop, doing
another phy_configure_link() in the eth driver would overwrite
that.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
fixed link mode is a mode where we don't comunicate with the phy,
therefore we don't need it in other phys as the generic phy_mii one.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Also increase regulator init priority so that ethernet vdd is
turned before PHY initialization
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Re-use the workqueue instead of having dedicated thread for handling
interrupts. This reduces memory usage and complexity.
Furthermore adds an auto mode for 100BASE-T1 negotiation.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
The Intel i226 Ethernet Controller is a PCIe Gen 2 one-lane modular
endpoint device that integrates a GbE Media Access Control (MAC) and
Physical Layer (PHY) port. This driver provides support for MAC and
DMA-specific initialization and runtime TX/RX operations.
Key features:
- MSI-X interrupts for TX/RX DMA channels.
- Multiple TX/RX DMA channel support with exclusive bottom-half.
- Implements a circular descriptor ring architechture with
producer-consumer semantics for high performance pkt processing.
- Full duplex support for 10/100/1000 Mbps.
- Half duplex support for 10/100 Mbps.
- Auto-negotiation for 10/100/1000 Mbps.
- MTU customization for flexible packet sizes.
- MAC address filtering based on:
- Random MAC generation.
- Local-mac-address mentioned in device tree.
- EEPROM pre-programmed mac address.
- Setting mac address via net shell.
- Support for multiple Ethernet interface instances.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>
The Ethernet device model consists of multiple subsystem components, such
as MDIO, PHY, MAC and PTP_CLOCK. These components are mapped into a single
PCIe BAR location with same base address.
This platform driver retrieves the MMIO mapping details and provides a
framework to share it with all the child subsystem components. This
approach avoid the duplicate remapping, ensures efficient re-use of
MMIO mappings across related devices.
Example device tree structure for first ethernet instance:
parent0: parent0 {
compatible = "intel,eth-plat";
interrupt-parent = <&intc>;
vendor-id = <0x8086>;
device-id = <0xXXXX>;
igc0: igc0 {
compatible = "intel,igc-mac";
/*
* MAC specific properties.
*/
status = "okay";
};
mdio0: mdio0 {
compatible = "intel,igc-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy";
/*
* PHY specific properties.
*/
reg = <0x0>;
};
};
};
This framework is modular and re-usable for other PCIe based Ethernet
devices. It can also be extended to support additional platform specific
information shared across child nodes.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Add support for disabling autonegotiation to the cfg_link callback, as
with the phy_mii driver.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The driver previously could enter an infinite loop if the PHY software
reset failed to complete, which could happen due to hardware reset
issues or MDIO bus problems. Add a timeout of 1000 iterations so we
report an error in this scenario rather than causing a lockup.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
For GPIOs driving active-low signals, such as the VSC8541's reset pin,
they are supposed to be declared as active low in the device tree, and
set to 1 to assert and 0 to clear. Change the driver as such so that it
does not leave the PHY stuck in reset when so configured.
Also changed all in-tree board DTS files for this PHY to properly
declare the reset GPIO as active low.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The internal register read/write functions used uint32_t for the values
even though the registers are only 16 bits wide, resulting in a bunch of
casting. Change the internal functions to use uint16_t and wrap them for
the external read/write API which uses uint32_t.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The driver was not enabling the MDIO bus before trying to access
registers. Added enabling and disabling the bus around PHY register
accesses.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Fixed some build warnings in the driver from previous changes by
removing an unused variable and hooking up the cfg_link function. Also
removes some implicit boolean conversions.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
use mutex to protect page register
phy_mc_vsc8541_get_link got removed from
phy_mc_vsc8541_link_cb_set so, that
phy_mc_vsc8541_link_monitor (own thread)
is the only one to change data->state
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
- implement configure link
- support half duplex
- use defines from mii.h
- fix check ret vals
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Previously, phy_monitor_work_handler() would return early without
rescheduling the delayed work if the callback (cb) was not set,
causing the periodic monitoring to stop. This change ensures that
k_work_reschedule() is always called, even when cb is NULL, so
monitoring of the PHY state continues.
This prevents the monitor from being inadvertently stopped and
ensures consistent behavior regardless of callback registration.
This issue was observed during testing with the evb-lan8670-rmii
(an external LAN8670 PHY) connected to the SAME54 Curiosity Ultra
platform.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Call mdio_bus_enable() and mdio_bus_disable() during clause 22 register
read/write operations. Previously, these APIs were not invoked, which
could lead to improper MDIO bus handling.
This issue was observed during testing with the evb-lan8670-rmii
(an external LAN8670 PHY) connected to the SAME54 Curiosity Ultra
platform.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
C45 direct registers access is only supported by the LAN865x internal PHY,
not by the LAN867x external PHY, even though the MAC supports it. Restrict
C45 direct register access to the LAN865x internal PHY. The LAN867x
external PHY supports C45 registers only via indirect access through C22
registers.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Align the LAN865x driver module initialization priority with the default
priorities of MDIO and PHY drivers. The microchip_t1s PHY driver supports
both LAN865x internal PHY and LAN867x external PHY. It was observed that
the microchip_t1s driver initialization priority did not match the
priority sequence used by the GMAC driver when the evb-lan8670-rmii (an
external LAN8670 PHY) was connected to the SAME54 Curiosity Ultra
platform, leading to potential initialization order issues. This change
ensures the correct initialization sequence for reliable operation.
The initialization priorities of the microchip_t1s and mdio_lan865x
drivers are now set to the default values used in Zephyr. The LAN865x
driver init priority is updated to the most appropriate value so that the
microchip_t1s init priority aligns with all MAC drivers, maintaining the
correct initialization sequence.
Since the microchip_t1s driver can be used by many MAC drivers, keeping
the default priority provided by Zephyr is a good approach. Instead,
setting a specific priority for the eth_lan865x driver is more appropriate
to ensure proper initialization order.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Add support to generate the random MAC if 'zephyr,random-mac-address'
is set,uses 'local-mac-address' from DT if available, or falls back
to a default Xilinx OUI-based MAC with zeroed bytes
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
don't use global buffers for reg_read and reg_write,
so we only need to rely on the spi drivers lock and
don't have to use our lock.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
It is not possible to build anymore in that mode, so we do not
need to support it in this driver cmake files.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Current Implementation to write to MAC_MDIO_ADDRESS causes CR to be
set to 0. This leads to the divide always being 42 (on FRDM_MCXN947)
so, by default the clock is running at ~3.6MHz which is out of spec
range (1.0-2.5MHz)
This stops the do_transaction function from overwriting CR.
It also saves off the CR register before DMA reset
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Clean up unused variable 'ret' and 'link_state' in eth_xilinx_axienet.c to
improve code clarity.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Clean up unused variable 'rand_mac_addr' in eth_sensry_sy1xx_mac.c to
improve code clarity.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Update the driver to handle -ENOSYS from phy_configure_link(), which is
now returned when the cfg_link callback is missing (e.g., in fixed-link
PHYs).
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
use DT_INST_PROP_OR for local-mac-address, so
that it is not required to be set in dt, as there are
other ways to se the mac address.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
make sure, that zephyr,random-mac-address
has a higher prio, than local-mac-address, as
documented in ethernet-controller.yaml.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
make sure, that zephyr,random-mac-address
has a higher prio, than local-mac-address, as
documented in ethernet-controller.yaml.
Also make sure, that no vaild mac address
doesn't lead to init fail, as it can still be
set later via set_config.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Use signed variable for negative error codes so that potential errors
are actually detected and returned properly.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use the HWINFO API for getting the unique mac address, and use the
pre-existing hardcoded macros as fallbacks if hwinfo is not implemented
properly.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
