move dev init into iface init. By registering the
uart pipe at the end of the iface init, we also no longer
need to check in the callback if the iface init was done.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Added support for the MDINT interrupt pin, through which the PHY signals
the MCU when certain link events occur.
Signed-off-by: Robert Khanafiev <robert.khanafiev@fischer-electronic.com>
The link was monitored in a separate thread that was initialized with
an incorrectly defined stack. This caused an exception on some systems.
The thread has been replaced with a dedicated workqueue.
Signed-off-by: Robert Khanafiev <robert.khanafiev@fischer-electronic.com>
When switching ETHA operating modes, the transition may fail to
complete if the PHY-derived clock is unexpectedly stopped, leaving
RMAC in an indeterminate state.
If the requested mode is not reached within the timeout, enable
RMAC emergency clock recovery (MIOC0) to flush internal RMAC state
and temporarily switch to a free‑running clock. Wait for the ETHA
mode transition to complete, then restore normal PHY clocking.
This improves robustness of RMAC/ETHA mode transitions without
requiring a full device reset.
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
For devices that does not have interrupt pin, default to polling mode
instead.
Polling period can be configured through
CONFIG_ETH_W5500_POLL_PERIOD.
Signed-off-by: Aiman Mazlan <mohammad.aiman@stratusauto.com>
move net_eth_mac_load into iface init, that way we don't
need to save the mac address in the data struct.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The boards and shield using W5500 chip on latest release (v4.4)
require higher stack size to function
Signed-off-by: Krisztian Szilvasi <krisztian@atym.io>
native_tap only queued TX timestamp callbacks for gPTP packets, which
left PTP SO_TIMESTAMPING socket traffic without TX timestamps.
Add host-clock packet timestamp updates in native_tap TX/RX paths, queue
TX timestamp callbacks when net_pkt_is_tx_timestamping() is set (while
preserving gPTP behavior without double-queueing), and propagate
SO_TIMESTAMPING TX/RX flags for AF_PACKET packets in net_context.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
RM0481 Rev 4 documents the Ethernet PTP timestamp clock as a dedicated
reference clock (`clk_ptp_ref_i`), not the `eth_hclk` bus clock.
Table 115 ("Kernel clock distribution overview", p. 470/3154) lists
`ETH (ptp)` on `pll1_q_ck`, and the IEEE 1588 section states that the
64-bit PTP time is updated from `clk_ptp_ref_i`.
Add an explicit `mac-clk-ptp` clock for STM32H5 sourced from
`STM32_SRC_PLL1_Q`, use that clock rate for PTP addend programming.
Because this change introduces source-clock configuration for STM32
Ethernet clocks, update the STM32H7 DWMAC path as well: use
`clock_control_configure()` for source clocks such as `eth-ker`, while
keeping `clock_control_on()` for gated clocks.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
By default the DWMAC ethernet controller is configured
to drop all multicast packets. Currently, HW filtering is
not supported, so we need to configure the controller to
pass all multicast packets.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add ethernet_api start() and stop() callbacks to support the Zephyr
net iface down/up workflow.
stop() disables MAC RX, stops DMA RX and TX channels,disables MAC TX,
and resets all descriptor ring indices.
start() seeds the RX DMA ring and enables MAC RX and TX.
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
The Transmitter Configuration register (offset 0x408) TX enable bit is
bit 28 as per the AXI Ethernet Subsystem product guide (PG138), not bit 11.
Fixes: 4342d7108b ("drivers: ethernet: Add Xilinx AXI Enet driver")
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
net_if_carrier_off() should be called before
phy_link_callback_set(), as itside it, the carrier could be
already changed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
net_if_carrier is to be used independently of the
administrative state (start and stop of the ethernet_api).
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Some systems can have board layout that can cause PHY
reset to be slower. So add more checkes to make sure
PHY is completely out of reset. We basically check
1) Power down bit from BMCR register
2) Reset bit from BMCR register
3) Factory Bit in OMSO register
Tested:
Verified that on a system with slow PHY
reset, the bit verification logic helps
ensure PHY is out of reset.
If the PHY takes longer thann 0.5s, then the
PHY bit checking logic helps surface the problem.
Signed-off-by: Nikhil Namjoshi <nikhilnamjoshi@google.com>
As net_if_set_link_addr() is now already done by the
overlaying net_mgmt, we no longer need to do it
in the drivers
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
In a board I am trying to bring up(RA6M3 + LAN9370),
the phy callback got executed before net_if_carrier_off(),
which meant the OS thought permanently the interface was down.
Moving the net_if_carrier_off() before the callback registration
seems to fix the issue.
Signed-off-by: Paolo Bazzanella <pbbazzanella@gmail.com>
Add support for configuring the MAC based on the PHY link state.
This allows the driver to properly set the speed and duplex
settings of the MAC when the link state changes.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
this is a leftover from when the vlan ifaces were not
virtual ifaces. With this currently in we would deactive lldp
on the main iface everytime a vlan is deactivated.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
ALso simplify link status update logic.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
remove redundant net_pkt_set_iface() it is already set in
net_recv_data() and net_pkt_rx_alloc_with_buffer().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add Ethernet support including:
- Board initialization code with PHY reset handling
- Device tree definitions for ethernet
- PHY link state tracking fixes in ethernet driver
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Track success explicitly and only report timeout when no matching PHY ID
was found after all retries.
Extend the Motorcomm YT8521 PHY driver to support YT8531 chip.
The YT8531 is compatible with YT8521 and shares the same register
layout and configuration interface.
- "motorcomm,yt8521" for YT8521
- "motorcomm,yt8531" for YT8531
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
