RIF configuration is now done at soc init time in a centralized
way so it is no more necessary for drivers to perform this
configuration.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The default configuration for all STM32 microcontrollers in HAL is
to replace the ehternet MAC address with the address configured in
replace address zero. In "modules/hal", Grep for:
macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
But this is a bad thing for bridging. Since Zephyr ethernet LL code
always writes the source address, this patch has no impact on normal
operation. And has the benefit of maintaining the source MAC address
of bridged packets.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
This commit introduces helper functions to avoid having large
#if DT_HAS_COMPAT_STATUS_OKAY ... #else blocks,
improving readability.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
The reset gpio field was in the config structure but was not coded
into the initialization path. So, add the appropriate code to handle
the gpio setup when it is defined in the device tree.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
Extend the lan9250 driver to support using a local administered
unicast random mac address during init. This follows the device tree
settings for zephyr_random_mac_address from other ethernet drivers
for the added support.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
The irq_lock area including net_pkt_rx_alloc_with_buffer() was causing
error "Context switching while holding lock!".
Actually we didn't have any hardware access to protect in netc_eth_rx,
so just removed irq_lock.
Fixes#99694
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
moves the fixed link functionality of the
generic ethernet phy into its own driver.
This makes both drivers more readable and
efficient.
Also makes it easier to use the normal generic
phy as a base for a vendor specific driver, as
the fixed link functionality is not needed on
them.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
auto negotiation might already be finished when we
check the link status, therefore check directly
instead of waiting 100 ms.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The latched bits are defined in the ethernet specification,
as the only latched bit, that we use, is the link status, improve
the code for it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Added PTP timestamping support in NETC ENETC host driver for no-tag
supported NETC switch.
On RX path, extended descriptor is used on host (pseudo MAC) to get
timestamp writeback.
On TX path, TX timestamp response should be enabled on host (pseudo MAC).
After TX, writeback TX timestamp ID should be updated to tx pkt fifo.
Once RX path received TX timestamp response, match TX timestamp to tx
pkt in fifo with the timestamp ID.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
For NETC switch with tag support, PTP timestamping had already been
supported in tag driver.
This patch is to add PTP timestamping support for no-tag supported switch.
Timestamp functions are implemented and exported for host driver to
handle.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Converted to use NETC_PTP_TIMESTAMPING_SUPPORT for PTP timestamping.
PTP timestamping is needed only when NET_L2_PTP and PTP_CLOCK_NXP_NETC
are selected.
Used default 16 bytes for ETH_NXP_IMX_RX_RING_LEN for PTP timestamping
because RX extended descriptor would be used.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
PTP timestamping should be enabled only when NET_L2_PTP and
PTP_CLOCK_NXP_NETC are selected. And NET_PKT_CONTROL_BLOCK
is required for PTP timestamping code.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Rework the Atmel SAM GMAC driver to read a MAC address from the provided
NVMEM cell instead of using I2C commands directly.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The native_sim Ethernet driver was still using POSIX symbols,
so convert these to use Zephyr ones.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
remove mdio_bus_enable/mdio_bus_disable, as they are no
longer needed and make the mdio api simpler.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Add PHY driver for Motorcomm YT8521 which is used on FRDM_IMX93 board.
Signed-off-by: Hongbo Wang <hongbo.wang@nxp.com>
Signed-off-by: Jiafei Pan <jiafei.pan@nxp.com>
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.
Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Replace 'if (ret)' with 'if (ret < 0)' in the Microchip T1S PHY driver.
This change follows the legacy coding style commonly used in Zephyr
drivers, where error conditions are checked explicitly against negative
values. The affected functions do not return positive values, so this
modification does not change functionality. No functional change intended.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Configure the link status in the Link Status Control register for
LAN8670/1/2 Rev.D0 PHYs, depending on whether PLCA or CSMA/CD mode
is enabled. When PLCA is enabled, the link status reflects the PLCA
status. When PLCA is disabled (CSMA/CD mode), the PHY does not support
autonegotiation, so the link status is forced active by setting
the LINK_STATUS_SEMAPHORE bit.
The link status control is configured:
- During PHY initialization, for default CSMA/CD mode.
- Whenever PLCA configuration is updated.
This ensures correct link reporting and consistent behavior for
LAN867x Rev.D0 devices.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Add support for the LAN8670/1/2 Rev.D0 10BASE-T1S PHYs from Microchip.
The new Rev.D0 silicon requires a specific set of initialization
settings to be configured for optimal performance and compliance with
OPEN Alliance specifications, as described in Microchip Application Note
AN1699 (Revision G, DS60001699G – October 2025).
https://www.microchip.com/en-us/application-notes/an1699
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
The old native_posix ethernet was renamed to native_tap in
78f800642a
and its old kconfig options deprecated at the time (in 4.2)
Let's remove them now.
Note in this commit we move the defaults into their right place.
Defaults were set in the deprecated options so we could both
have the defaults and allow users to keep using the old options.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add the support of the stm32mp13 ethernet:
- Adapt to HAL API
- Add support of a memory region in DT for descriptor and buffers
- Add support of PHY with/without crystal 50MHz
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Signed-off-by: Arif Balik <arifbalik@outlook.com>
The typedef ETH_TxPacketConfigTypeDef is used consistently in the driver.
However, some instances of ETH_TxPacketConfig have not yet been replaced.
On the STM32MP13 series, the ETH_TxPacketConfig typedef is no longer
defined. This cleanup ensures compatibility and consistency.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Add basic support of the LAN8742 RMII phy. The driver is inspired
from the phy_mii generic driver, with the support of a GPIO reset.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
'GMAC_QUEUE_NUM' is a value of 'num-queues' for the first GMAC
instance getting from the device tree. It is used directly or
indirectly (by GMAC_PRIORITY_QUEUE_NUM) for defining and
initializing 'struct eth_sam_dev_data' with a value from Kconfig
(GMAC_ACTIVE_PRIORITY_QUEUE_NUM).
As there will be a big change for applying the corresponding
num-queues for each GMAC 'struct eth_sam_dev_data', here just
keep it as is. Adding the BUITD_ASSERT to make sure the array
queue_list[] is large enough for all GMAC instances.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add variable 'random_mac_addr' for 'zephyr,random-mac-address' from
device tree. Update generate_mac() to get random MAC address for each
GAMC interface with the 'zephyr,random-mac-address' property.
Signed-off-by: Tony Han <tony.han@microchip.com>
Deprecate the 'ETH_SAM_GMAC_MAC_I2C_EEPROM' for the 'mac-eeprom' option,
Limite it to be used when there's only one activated GMAC instance.
Signed-off-by: Tony Han <tony.han@microchip.com>
As jumbo frame size is not supported by the networking subsystem, only
max_frame_size 1518 and 1536 can be used. The Frame size 1536 would
allow for packets with a vlan tag, so enable GMAC_NCFGR_MAXFS when
NET_VLAN is configured.
Signed-off-by: Tony Han <tony.han@microchip.com>
To allow every interface be initialized properly when there are more than
one instance, remove the static variable "init_done" which is used to make
the initialize procedure only be done once.
Signed-off-by: Tony Han <tony.han@microchip.com>
