There were some driver bindings issues for the davicom dm8806 driver:
- Missing type for reg-switch binding
- Missing required: true for int/reset gpios
- Fix macro for reg-switch
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Calculate the EBO properly, so the total frame written to TX FIFO
does not exceed maximum Ethernet frame length.
Makes the TCP stack to work properly, otherwise packets > 1472 are dopped,
as they would be padded by 64 more bytes
and hence exceed maximum Ethernet frame size.
Signed-off-by: Maciej Panek <panekmaciej@outlook.com>
Refactors the code in adin2111_offload_thread
to improve its readability. Adds code to read RX FIFO
in OA mode until it is empty.
Signed-off-by: Maciej Panek <panekmaciej@outlook.com>
This commit adds basic support for KSZ8463/KSZ8463F chips to the
dsa_ksz8xxx.c driver.
These chips have limited register compatibility with other members
of the KSZ8XXX family - their registers are 16 bits wide as opposed
to the 8-bit registers supported by the driver for KSZ8794 and
KSZ8863. Following the general logic of the existing code,
the 16-bit registers of KSZ8463 are split into 8-bit halves.
For the KSZ8463F chip, it is assumed that both ports are used
in Fiber mode.
A new configuration option, CONFIG_DSA_KSZ_PORT_ISOLATING, has been
added to isolate traffic between DSA slave ports.
The driver has been tested on a custom board with an STM32F7 SoC.
Signed-off-by: Aleksandr Senin <al@meshium.net>
This is to support handling pseudo MAC during initialization, but not
to support DSA master port. Current driver supports DSA with limitation
that only switch function is available without management via DSA master
port. DSA master port support is TODO work.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
NXP i.MX NETC is a TSN capable Ethernet IP. It may support
ENETC MACs, or/and multiple ports switch.
The ENETC MAC was handled by eth_nxp_imx_netc driver.
This DSA driver is to support NETC switch device.
Current driver supports DSA with limitation that only switch
function is available without management via DSA master port.
DSA master port support is TODO work.
Take i.MX RT1180 NETC hardware as an example.
+--------+ +--------+
| ENETC1 | | ENETC0 |
| | | |
| Pseudo | | 1G |
| MAC | | MAC |
+--------+ +--------+
| zero copy interface |
+-------------- +--------+----------------+ |
| | Pseudo | | |
| | MAC | | |
| | | | |
| | Port 4 | | |
| +--------+ | |
| SWITCH CORE | |
+--------+ +--------+ +--------+ +--------+ |
| Port 0 | | Port 1 | | Port 2 | | Port 3 | |
| | | | | | | | |
| 1G | | 1G | | 1G | | 1G | |
| MAC | | MAC | | MAC | | MAC | |
+--------+-+--------+-+--------+-+--------+ |
| | | | |
NETC External Interfaces (4 switch ports, 1 end-point port)
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit fix the pin function configuration for mii and rmii
setting of Renesas RA8 ethernet driver
Correct pin function setting for mii is
PFENET = (uint8_t)(0x1 << R_PMISC_PFENET_PHYMODE0_Pos);
and rmii is:
R_PMISC->PFENET = (uint8_t)(0x0 << R_PMISC_PFENET_PHYMODE0_Pos);
Change code to intialize ping in driver init function, change
method of getting and checking via enum index of device tree.
Add build assert for invalid phy type.
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Energy efficient mode is the feature of the DM8806 described in the
EEE 802.3az Energy Efficient for reducing power consumption. For unknown
reason it seams to not working correctly with all endpoints and sometimes
the network randomly fails when this mode is on. Thus it is now possible to
turn off it in compile time by KConfig option:
PHY_DM8806_ENERGY_EFFICIENT_MODE if in case of network problems
Signed-off-by: Robert Slawinski <robert.slawinski.ext@indurad.com>
Allow DSA_TAG_SIZE to be set based on the size determined by Kconfig
and the enabled switch hardware.
This fixes support for the KSZ8863 which also has a tail tag of
one byte.
Signed-off-by: Bas van Loon <s.r.vanloon@ziggo.nl>
SMI bus error check mechanism is preventing the host SMI bus to be
interferred by noise on board level. Current implementation is checking
if data which is writing to/reading from the PHY has correct CRC sum.
If not, then writing/rading process is repeated by the number of
attempts defined in the KConfig. If repeating transmission will fail
by the numbers of ettemps defined in KConfing, drivers returns an
error.
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
The struct ring_buf is renamed to struct ring_buffer to be able to coexist
with the sys/ring_buffer.h header file.
Signed-off-by: Måns Ansgariusson <Mansgariusson@gmail.com>
Implement lan865x mdio driver to provide interface between lan865x MAC
driver and internal PHY driver phy_microchip_t1s.c. This driver is needed
to support the driver architecture followed.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Implement c22/c45 registers mdio read/write APIs for the lan865x mdio
driver to provide interface to the lan865x internal PHY driver.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Fix the style formatting of oa_tc6.c and oa_tc6.h files using
clang-format utility.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Remove internal PHY initialization part as the phy_microchip_t1s.c
driver will do the internal PHY initialization.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Fix the style formatting of eth_lan865x.c and eth_lan865x_priv.h files
using clang-format utility.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Add support for LAN8670/1/2 Rev.C2 as per the latest configuration note
AN1699 released (Revision E (DS60001699F - June 2024)) for Rev.C1 is also
applicable for Rev.C2. Refer hardware revisions list in the latest AN1699
Revision E (DS60001699F - June 2024).
https://www.microchip.com/en-us/application-notes/an1699
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Add support for LAN8650/1 Rev.B1. As per the latest configuration note
AN1760 released (Revision F (DS60001760G - June 2024)) for Rev.B0 is also
applicable for Rev.B1. Refer hardware revisions list in the latest AN1760
Revision F (DS60001760G - June 2024).
https://www.microchip.com/en-us/application-notes/an1760
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
10BASE-T1S PHYs can operate in either CSMA/CD or PLCA mode. PLCA mode
needs some set of parameters like node id, node count, max burst count,
burst timer and TO (Transmit Oppertunity) timer to be configured. OPEN
Alliance TC14 specification defined a set of PLCA registers to configure
PLCA mode. The below APIs are implemented for PLCA mode.
genphy_set_plca_cfg() - to configure PLCA settings.
genphy_get_plca_cfg() - to get the configured PLCA settings.
genphy_get_plca_sts() - to get the PLCA status like active or inactive.
These APIs are implemented as generic library so that all 10BASE-T1S
PHYs can use these APIs to configure/access PLCA settings to avoid
duplication of code.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Refactor and merge the SoC support files for the Atmel SAM E70 and SAM V71
product series. These SoCs are part of a larger product family (SAM
E70/S70/V70/V71) and share a common set of peripherals.
Support for the two remaining product series (SAM S70/V70) is not part of
this refactoring as these will require further additions to the Atmel HAL.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Simplifies GPIO reset logic in `phy_mc_ksz8081_reset()` by introducing
a dedicated function, `phy_ksz8081_reset_gpio`. If this function returns
`-ENODEV`, it will fall back to using a command-based reset instead.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Simplifies error handling in `phy_mc_ksz8081_get_link()` by
centralizing mutex unlocking with a `done` label.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This implements to generate the MAC address of the device UUID.
The UUID is hashed to reduce the size to 3 bytes.
Ideas taken from eth_nxp_enet.c
Adding dependencies on: HWInfo and CRC
Signed-off-by: Adib Taraben <theadib@gmail.com>
first check if the chip has a hosh module to futher filter MAC addresses
if not then enabling the pass through for all multicast protocols
Signed-off-by: Adib Taraben <theadib@gmail.com>
This patch fixes an assert in net_buf_simple_add() function when the
lan_9250 driver would add previously added data to the net buffer
on receiving large (>128 bytes) packat. This fix was to use the frags
field of the net_buf structure instead.
Tested with a nRF54L15 DK and eth3 click board (with nordic connect sdk
2.8.0 and this patch).
Signed-off-by: Balaji Srinivasan <balaji.srinivasan@autostoresystem.com>
Currently, there is a small race window where we can miss an interrupt.
Right after we're done reading the RX buffer but just before decrementing
the RX counter to zero, the ENC28J60 may receive a packet. The chip will
raise an interrupt, but the line is still asserted. That means that the
callback will not be invoked since it is edge-triggered.
To avoid that, disable interrupts on the chip itself before processing
the RX buffer.
In fact, the ENC28J60 datasheet specifically says:
"After an interrupt occurs, the host controller should
clear the global enable bit for the interrupt pin before
servicing the interrupt. Clearing the enable bit will
cause the interrupt pin to return to the non-asserted
state (high). Doing so will prevent the host controller
from missing a falling edge should another interrupt
occur while the immediate interrupt is being serviced.
After the interrupt has been serviced, the global enable
bit may be restored. If an interrupt event occurred while
the previous interrupt was being processed, the act of
resetting the global enable bit will cause a new falling
edge on the interrupt pin to occur."
This is also what is being done in the Linux driver [1].
[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1126
Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
The enc28j60 errata sheet says:
"The Receive Packet Pending Interrupt Flag
(EIR.PKTIF) does not reliably/accurately report
the status of pending packets."
"In the Interrupt Service Routine, if it is unknown if
a packet is pending and the source of the interrupt
is unknown, switch to Bank 1 and check the value
in EPKTCNT.
If polling to see if a packet is pending, check the
value in EPKTCNT."
A workaround has already been implemented inside of eth_enc28j60_rx().
But checking PKTIF before calling eth_enc28j60_rx() completely defeats
the purpose of the workaround. Do not check it.
Moreover, clearing ENC28J60_BIT_EIR_PKTIF is useless since it is
automatically cleared once all packets are read. So remove that check
and clarify comment.
Also please refer to the Linux driver [1].
[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1090
Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
Add a get_config function for this driver as specified in the
Ethernet subsystem API. The implementation supports querying
the hardware checksum generation capabilities of the specified
GEM device instance. This prevents the transmission of packages
without a valid checksum for protocols such as ICMP, as the
hardware only supports IPv4/IPv6 TCP and UDP checksum generation.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Compilation will fail if both adin2111 and adin1100 are used
at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This PR adds support for LAN9250 spi ethernet controller.
This driver is tested on the Mikroe ETH Click 3
https://www.mikroe.com/eth-3-click
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
On the interrupt handling, one thread per driver instance is involved
into monitoring the semaphor, sends inside the gpio callback triggered
by the gpio interrupt. Each time, when the link parameters are change,
the DM8806 is generating the gpio interrupt. After getting semaphor,
the application callback function which was linked during initialization
process is called to get the new link parameters with standard API
calls
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
New driver for Davicom DM8806 PHY. Driver is using standar mdio API
to manage the DM8806 switch controller. Register access needs the
PHY addres or switch address to be one of five possible values, since
DM8806 has built-in five PHY's. These values should be defined in the
application .dts file. One DM8806 ethernet port must corresponds with
one ethernet PHY node with two properties for ethernet port: one for
PHY address and one for switch address - <reg> for register access from
Internal PHY Register area and <reg-switch> for register access from
Switch Per-Port Registers area. Device tree example below:
example device-tree:
dm8806_phy: ethernet-phy@0 {
reg = <2>;
reg-switch = <8>;
compatible = "davicom,dm8806-phy";
status = "okay";
davicom,interface-type = "rmii";
reset-gpio = <&gpiod 2 GPIO_ACTIVE_LOW>;
interrupt-gpio = <&gpioc 1 GPIO_ACTIVE_HIGH>;
};
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
This commit is to enable Ethernet drivers support on Renesas RA
MCU, first target support is the Renesas RA8 series
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
The ICS1894 phy AN_COMPLETE bit is latched high, this make the
BMSR first read return incorrect status of the AN state, update
one more BMSR read to ensure all latched bit is clear and BMSR
return actual status of the phy chip
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
The _nxp_enet_dma_buffer_section is configured to __nocache area.
That makes the RxPkt performance very low (<= 50Mbps). By defining
it to the cacheable area, the RxPkt performance is >10x better.
Example with Zperf:
DUT command - zperf udp download 5001
PC command - iperf -u -c 192.0.2.1 -p 5001 -b 800M
Signed-off-by: Shrek Wang <shrek.wang@nxp.com>
- Move selection of CONFIG_PINCTRL from soc to individual
drivers
- in accordance with issue #78619
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
