Add the microchip,rgmii-delay binding for KSZ9131 PHYs and use it
on the SAMA7G54-EK board DTS.
GMAC0 on SAMA7G54-EK is connected to a KSZ9131 PHY over RGMII and
requires internal delay configuration equivalent to rgmii-id for
reliable gigabit operation.
Add KSZ9131 RGMII DLL delay configuration using Clause-22 indirect
MMD access.
The KSZ9131 PHY uses MMD device 2, registers 76 and 77, to control
RXC and TXC DLL delay bypass. Configure these registers according
to the requested RGMII delay mode:
- none
- id
- rxid
- txid
Delay setting would be skipped for variants that do not support RGMII
like KSZ9131MNX
Signed-off-by: Balaji Vasudevan <balaji.vasudevan@microchip.com>
These macros are private to the net subsystem, let's not use them in
drivers
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add a Kconfig option to configure the RX refill thread priority.
The default is set to 0, which is the same as the previous hardcoded
value. This allows users to set a different priority if needed.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Thread priority was passed to options argument of k_thread_create,
instead of the priority argument.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
H5 series SoCs have a similar Ethernet MAC to the H7 series,
but with some differences with respect to configuration of phy
interface type. As they use a Cortex-M33 core, they have no cache,
so that dma descriptors are always in non-cached memory.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
H7RS series SoCs have a similar Ethernet MAC to the H7 series,
but with some differences with respect to configuration of phy
interface type.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Configure phy connection type to value specified in device tree.
Utilize definitions from STM32 Low-Level APIs instead of open coding
values.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
1. adjusted enet_qos driver to cope with features missing on mcxa577
2. enabled enet_qos support
3. verified samples/net/zperf
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Mode is no longer fixed to full-duplex, it is set to half-duplex or
full-duplex in PHY callback.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Plca nodes with node_id not 0 do not manage transmit windows and
should therefore not be required to provide plca_node_count.
This change makes plca_node_count optional for (node_id != 0)
and if omitted sets the default value to 0.
The behaviour for node with id 0 stays the same.
Signed-off-by: Julian Paul <julian.paul@siemens.com>
This adds initial support for the CH32V ethernet peripheral.
The driver supports both internal and external PHY configurations.
Signed-off-by: James Bennion-Pedley <james@bojit.org>
Fix warnings about using char * for %p argument in cbprintf. It's
recommended to cast it to void * because it may cause misbehavior
in certain configurations.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds a Kconfig option to detect if checksum offloading
is supported by any driver and one to activate it.
Main benefit is that `net_if_need_calc_rx_checksum()` and
`net_if_need_calc_tx_checksum()` are now inline and therefore the
compiler can optimize more, when checksum offloading is not supported.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Update the dwmac_stm32h7x ethernet driver to use the same default
MAC address as the STM32 HAL driver.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Change return value of dwmac_platform_init to int and return error code
in case of failure. This allows to report errors from platform init and
fail the driver probe if platform init fails.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Set register bit GMAC_NCFGR.GBE to configure GMAC for 1000Mbps operation.
Gigabit mode is not supported by SAM E70/S70/V70/V71 family, it is
supported by SAMA7G54.
Signed-off-by: Tony Han <tony.han@microchip.com>
The initialization priority was hardcoded to 0. However, the initialization
takes a relatively long time (1 to 2 seconds on RW612). With this change,
the initialization priority properly follows CONFIG_ETH_INIT_PRIORITY.
Signed-off-by: Sebastiaan Merckx <sebastiaan.merckx@verhaert.com>
WIth the rework of the vlan handeling, the iface init
will only be executed once per instance, so we don't need
that check anymore.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit add phy driver support for Maxlinear GPY111. This driver
implements vendor specific behaviour rgmii delay time setup, which is
not present in the generic MII driver.
Signed-off-by: Nhat Ta <nhat-minh.ta.yn@bp.renesas.com>
In e6daacf3c9 the mayority of the
ethernet drivers code was changed to use the Zephyr native net_
prefixed symbols, but some were forgotten.
Without this fix/change the code still builds as we are by now setting
CONFIG_NET_NAMESPACE_COMPAT_MODE. But when this is not set, things
fail to build.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Promiscuous mode is enabled during initialization and cannot be
disabled at runtime.
Return -EINVAL when a request attempts to disable promiscuous mode.
Signed-off-by: Mori Fumita <mfumita@electromag.com.au>
ETHERNET_PROMISC_MODE is not advertised in
eth_nxp_enet_get_capabilities() even though promiscuous
mode is enabled during initialization when
CONFIG_NET_PROMISCUOUS_MODE=y.
Advertise ETHERNET_PROMISC_MODE in
eth_nxp_enet_get_capabilities() and accept
ETHERNET_CONFIG_TYPE_PROMISC_MODE in
eth_nxp_enet_set_config().
Signed-off-by: Mori Fumita <mfumita@electromag.com.au>
set the init prio of ethernet, mdio and the ethernet phy
to the same value, that way the prio from the dt is used.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This PR adds support for W6100 spi ethernet controller.
This driver is tested on the w6100-evb-pico
https://docs.wiznet.io/Product/Chip/Ethernet/W6100
Signed-off-by: Sayed Naser Moravej <seyednasermoravej@gmail.com>
hal_ret doesn't need to be assigned a value twice
before it is being used, so remove the unneeded first ones.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Due to checksum offloading, the checksum field of a packet must be
zero before sending it to packet to the ethernet controller,
otherwise the computed checksum will be incorrect.
If the packet is bridged, it already has the correct checksum in
place, which will cause the automatically computed checksum to
incorrectly become zero.
In this patch we give bridged packets the special attention they
need.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
integrate the mdio driver area into the
ethernet driver area. mdio itself is defined as part
of the ethernet specification.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Previously, the PHY driver always invoked the link state callback on
every check, even when the link state had not changed, and did not
properly synchronize access to the link state (issue #103826). This could
lead to spurious notifications and potential race conditions.
This patch:
- Calls the registered callback only when the link state actually changes.
- Logs link-up and link-down events correctly.
- Introduces a semaphore to protect the PHY link state.
- Updates link state in phy_mc_t1s_update_link_state() with proper
synchronization.
This ensures that both link state updates and callbacks reflect actual
changes, preventing unnecessary notifications and improving driver
correctness.
Fixes: #103826
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
menuconfig ETH_PHY_DRIVER is already inside a
`if ETH_DRIVER`, meaning it already depends on it,
therefore the condition for the default y is not needed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Call HAL_ETH_SetMDIOClockRange to set back the MDIO clock range
as it is set to 0 during the software reset.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Whenever a buffer descriptor or one of its properties is
referenced, either in macros, struct declarations or variable
declarations, use the spelling 'rx_bd'/'RX_BD'/'tx_bd'/'TX_BD'
instead of 'rxbd'/'RXBD'/'txbd'/'TXBD'.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Add fixes for ZynqMP-based targets:
- Consider the retrofitted 64-bit RX/TX buffer descriptor ring
base address registers which didn't exist on the Zynq-7000 yet.
- Properly tie off the unused set of RX/TX BD ring base address
registers as described in the ZynqMP TRM (UG1085 v2.4, chap. 34:
'GEM Ethernet', 'Programming Model', 'Initialize the controller',
p. 1064): indicate that there's no data to be transmitted via the
unused TX BD ring, and that no data can be placed via the unused
RX BD ring.
- Change the DMA layout: instead of having both the BD rings and
the packet buffers in non-cached memory or the Zynq's OCM, place
the BD rings in uncached memory but place the actual RX/TX packet
buffers in cached memory instead.
- Add the required cache maintenance operations for this layout.
- Select the required facilities for nocache memory and cache
maintenance support in the driver's Kconfig file.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
The e1000 Ethernet driver TX staging buffer is sized to NET_ETH_MTU
(1500 bytes), but the Ethernet L2 layer prepends headers (14 bytes
standard, 18 bytes with VLAN) before calling the driver's send function.
When transmitting MTU-sized packets, net_pkt_get_len() returns the full
L2 frame size (up to 1514+ bytes), causing a 14-18 byte out-of-bounds
write into adjacent RX buffers. This is remotely triggerable by inducing
large TX responses such as ICMP echo replies.
The RX staging buffer has the same issue - it is sized to NET_ETH_MTU
but receives complete L2 frames from the network which include headers.
Fix by sizing both TX and RX buffers to NET_ETH_MAX_FRAME_SIZE and
adding a defensive bounds check to the TX path.
Signed-off-by: Pavel Kohout <pavel.kohout@aisle.com>
Calling net_if_set_link_addr() is needed to update the link address
information of the interface.
Signed-off-by: Jeremy Truttmann <jetstreeam.code@outlook.com>
