This replaces the hard-coded vector table, as well as the
software ISR table created by the linker. Now both are generated
in build via script.
Issue: ZEP-1038, ZEP-1165
Change-Id: Ie6faaf8f7ea3a7a25ecb542f6cf7740836ad7da3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a new mechanism for generating interrupt tables which will
be useful on many architectures. It replaces the old linker-based
mechanism for creating these tables and has a couple advantages:
1) It is now possible to use enums as the IRQ line argument to
IRQ_CONNECT(), which should ease CMSIS integration.
2) The vector table itself is now generated, which lets us place
interrupts directly into the vector table without having to
hard-code them. This is a feature we have long enjoyed on x86
and will enable 'direct' interrupts.
3) More code is common, requiring less arch-specific code to
support.
This patch introduces the common code for this mechanism. Follow-up
patches will enable it on various arches.
Issue: ZEP-1038, ZEP-1165
Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In order to set breakpoints after waking up from sleep,
it is needed to save DR0/DR1/DR2/DR3 and DR6/DR7.
As DR4/DR5 are reserved or mapped to DR6/DR7, they are not saved.
Patch2 : Added compile time checks for debug build or soc_watch
build for Intel Energy analysis.
Patch3 : Avoid clobbering of edx.
JIRA: ZEP-1681
Change-Id: I62fbedca16953d57196420ecae4fb93c785bb4a5
Signed-off-by: Sarath R Nair <sarath.nandu.ramachandran.nair@intel.com>
This patch moves the include for the generated_dts_board.h inside of
the include/arch/arm/arch.h file. This was done to simplify the
includes required for files. Only two files will include the dts
generated include file directly: arch.h and the linker.ld
Change-Id: I2614f4fd4eeed2ab635a3264d7dac8b83f97b760
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We now use CMSIS for ARM Cortex-M SoCs so we can remove the last bits of
scs and scb.
Jira: ZEP-1568
Change-Id: I0c7c45b0321dc402ed594e9faffb5109922edcf0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Coverted:
_ScbMemFaultMmfarReset
_ScbBusFaultBfarReset
_ScbUsageFaultAllFaultsReset
To use direct CMSIS register access.
Also removed scb.h and references as there is no longer any code in it.
Jira: ZEP-1568
Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The previous code incorrectly used the value 0xfe to clear the mem and
bus faults. It attempted to handle the address register valid bits
separately, but reversed the bit order.
Jira: ZEP-1568
Change-Id: I240d072610af9979ca93c0081ed862df08929372
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Converted access to CFSR MMFSR, BFSR, and UFSR to use direct CMSIS
register access when printing out the values of those registers.
Jira: ZEP-1568
Change-Id: I7969bb81346327637140ec23d91422a6bfaef032
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Coverted:
_ScbBusFaultAddrGet
_ScbMemFaultAddrGet
To use direct CMSIS register access
Jira: ZEP-1568
Change-Id: Ic49b3ac3fc4fb63d413f273569c77f6539e4e572
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Pin number should be decremented by 8 if the pin
refers to the GPIOx_AFRH register.
Change-Id: I76e960f3b4adc3c2139ef5a88f15dbe98603228e
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native F3 Clock control driver.
Change-Id: I6f3ee44adb09adc52927eb4b05f8a829665eb96d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native L4 Clock control driver.
Change-Id: Ic0408d5f5ec66651d46d13dfaf447da2666367cd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32f3x soc.
Clean up will have to be done afterwards.
Change-Id: I20480579f12a6fc1f1f6a51589981ac3f1d63ef0
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32l4x soc.
Clean up will have to be done afterwards.
Change-Id: I979a4169148c5fe5a0693d182d2d17f9ffaf1c77
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch adds the base DTS support for the KW41Z Freedom board. The
initial set of changes include SRAM, FLASH, IRQ controller and LPUART
support.
Change-Id: Ic68c4959ddad0c5cfe70d5576a0e58372b93ec9d
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
This patch adds DTS support to the ARM CMSDK UART driver. The DTS
currently specifies the IRQ, IRQ PRIO, and base address of the port.
Change-Id: I8e5bc81c013958be4297d563495bf126b53a83a9
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the base DTS support for the V2M Beetle board. The
initial set of changes include SRAM, FLASH, and IRQ controller support.
Change-Id: I06685622b9c57ac358544c71350074ce06e3371e
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds all the necessary changes to enable use of DTS for
generating required build information.
Change-Id: Ia476fbb14c7d9d6b9db3340c73f599556a880da3
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch ifdef's out information that would be redefined by
information generated from DTS. This patch also fixes up the serial
drives to work properly with the DTS generated information.
Change-Id: I912ccf35be23c107705a4866e5a68b3b51154ffa
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support and related files for the NXP Kinetis
platform. The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms. The YAML files provide the definitions of
the contents of the DTS nodes.
The Kconfig changes were put in place to allow for the conversion of
existing drivers. Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.
Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support for using device tree configuration files for
configuring ARM platforms.
In this patch, only the FLASH_SIZE, SRAM_SIZE, NUM_IRQS, and
NUM_IRQ_PRIO_BITS were removed from the Kconfig options. A minimal set
of options were removed so that it would be easier to work through the
plumbing of the build system.
It should be noted that the host system must provide access to the
device tree compiler (DTC). The DTC can usually be installed on host
systems through distribution packages or by downloading and compiling
from https://git.kernel.org/pub/scm/utils/dtc/dtc.git
This patch also requires the Python yaml package.
This change implements parts of each of the following Jira:
ZEP-1304
ZEP-1305
ZEP-1306
ZEP-1307
ZEP-1589
Change-Id: If1403801e19d9d85031401b55308935dadf8c9d8
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Without this patch, the final linker script had a memory region defined
as:
RAM (wx) : ORIGIN = 0xA8006400, LENGTH = 55*1K - 0x20 +0x4
resulting on the wrong RAM length. Fix BSP_SHARED_RAM_SIZE definition
so the sum is always processed first.
Change-Id: I16b93adbaf27bb84b6e5d1ac433ef80f854b218c
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Arch-specific stuff shouldn't be in the toplevel Makefile,
forthcoming patches will soon introduce special interrupt
handling logic for other arches.
Change-Id: Ib5a86cbdf5b32ecfce9e5e234f7cbea2bc3ce9c1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This private data structure now no longer introduces a typedef or
uses CamelCase. It's not necessary to specify the size of extern
arrays, so we don't need a block of #ifdefs for every arch.
Change-Id: I71fe61822ecef29820280a43d5ac2822a61f7082
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit removes the local implementation of enter_arc_state, where
the ARC is instructed to sleep, using instead the QMSI 1.4 functions.
Change-Id: Id489ad53851be50fc5e50add698891fcfaef3abe
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
This flag is no longer necessary and TICKLESS_IDLE will be
enabled by default if SYS_POWER_MANAGEMENT is enabled.
Jira: ZEP-1325
Change-Id: Ic6cd4b8dc0a17c6a413cabf6509b215a4558318d
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
A new shared memory area has been added to the QMSI bootloader in
order to store the GDT in RAM reliably.
Add the new entry to the QUARK D2000 linker script and new
kconfig options:
* CONFIG_BSP_SHARED_GDT_RAM_ADDR to set the address location
of the GDT in RAM.
* CONFIG_BSP_SHARED_GDT_RAM_SIZE to set the size used by the
GDT in RAM.
This is only enabled when CONFIG_SET_GDT is NOT set.
Change-Id: Ie084079475853dce153dd9f3e88ad4a9784bdedf
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
A new shared memory has been added to the QMSI bootloader in order to
store the GDT in RAM reliably.
Add this new entry to the QUARK SE C1000 linker script and new kconfig
options:
* CONFIG_BSP_SHARED_GDT_RAM_ADDR to set the address location
of the GDT in RAM.
* CONFIG_BSP_SHARED_GDT_RAM_SIZE to set the size used by the
GDT in RAM.
Additionally, both BSP_SHARED_RAM_ADDR and BSP_SHARED_RAM_SIZE have been
renamed to BSP_SHARED_RESTORE_INFO_RAM_ADDR and
BSP_SHARED_RESTORE_INFO_SIZE respectively, in order to better resemble
what these options are for. All these configs are available
unconditionally.
Change-Id: I07ee8b440d4a3f5e9bdeb62441ff6a7bd6d4c153
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Bartlomiej Majka <bartlomiejx.majka@intel.com>
For the next QMSI release, the shared restore info address has been
modified to 0xA8013FDC .
Change-Id: I72eaef4f15f7ef6fb8e7eb9acd7d96451623e103
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Update the builtin QMSI code to 1.4 (RC2).
The below shim drivers were updated for API or interface changes:
- aio
- counter
- i2c_ss
- rtc
- wdt.
Also, arch soc specific power management code were updated.
Jira: ZEP-1572
Change-Id: Ibc8fae032a39ffb2c2c997f697835bc0208fd308
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
The entry point specified in the elf file should always point to
executable code, and not to the interrupt vector table. Pointing to the
vector table as the entry point in the elf file presents problems with
running the kernel against a debugger as the debugger starts the program
counter at the top of the interrupt vector table.
Change-Id: I76051f6e99a44bab72936670bead5fb8191a6ec7
Signed-off-by: Tim Nordell <tim.nordell@nimbelink.com>
Rename devices. For example, the two i2c devices in the
quark se sensor sub-system will have name string "I2C_0"
and "I2C_1", while the other two i2c devices accessible to
both x86 and arc will have name string "I2C_2" and "I2C_3".
This is valid only when you build arc binary.
It does not apply if you build x86 or arm binary. Similar change is
also made for GPIO and SPI.
Jira: ZEP-1588 ZEP-1614
Change-Id: Ibad4486e70e0aaf287763514a5a9d28b43bca094
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Added a linker script that shall be common to most riscv SOCs.
Linker script also accounts for execution in place in ROM, when
CONFIG_XIP is set.
Nonetheless, riscv32 SOCs (like pulpino) requiring a different
system layout can still define their own linker script.
Change-Id: I3ad670446d439772c29a8204e307ac79643dc650
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.
The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.
Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This is a zero-copy networking implementation of Ethernet driver.
Limitations:
- one shot PHY setup, no support for PHY disconnect/reconnect
- no support for devices with DCache enabled due to missing
non-cacheable RAM regions in Zephyr.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1492
Change-Id: Ib944f91193efbd12c1142b0bcf1f635388bf1b87
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added basic USART driver for Atmel SAM MCU family. USART is a very
comprehensive module, currently only basic features sufficient to
support printf functionality are implemented by this driver.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ia9710e4069243fb6c30de45953dfc1fe1266b63a
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Added common, internal, always available SAM HAL drivers: pmc, gpio.
Note: these drivers are meant to be used by other SAM drivers, not by
a user space program directly.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: I00cca358f27790dc94cf79f840584b85ff5191f6
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Added support for early SoC configuration which does not belong
conceptually to system initialization. ERASE, JTAG TDI pins are
currently configured here.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Id51adddb4c7cce22907af214461d75db83df129a
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added support for Atmel SAM E70 (Cortex-M7) MCU:
- Kconfig files
- device start-up code
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ide4fd5dadd94897303090a6507b8d048773b645e
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
As cpu_idle.S is the only bit of code that is using the SCB asm defines,
so to allow us to remove scb.h in the future lets move the defines that
are used just into cpu_idle.S
Jira: ZEP-1568
Change-Id: I3c3a6f145ec4c1a43f076d079d5fe1694c255b78
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
A number of SoCs clear out the Mem/Bus/Usage and Hard Fault exceptions
during init. Lets refactor that into a common function so we don't have
to keep duplicating it over and over.
Change-Id: Ida908a9092db37447abcf3c9872f36937982f729
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
