Xtensa port: Removed trailing spaces and unused macros. Reformatted comments.
Change-Id: I7f3fcba5d78c153c9b2830982e3ed6d5a1150c78 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
This commit is contained in:
Mazen NEIFER
Andrew Boie
parent
e861775ebb
commit
fb5299cd4a
2 changed files with 180 additions and 197 deletions
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@ -3,25 +3,23 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
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(FreeRTOS Port)
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This header is the primary glue between generic Xtensa RTOS support
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sources and a specific RTOS port for Xtensa. It contains definitions
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and macros for use primarily by Xtensa assembly coded source files.
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Macros in this header map callouts from generic Xtensa files to specific
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RTOS functions. It may also be included in C source files.
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Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
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architecture, using the Xtensa hardware abstraction layer (HAL) to deal
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with configuration specifics.
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Should be included by all Xtensa generic and RTOS port-specific sources.
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*******************************************************************************/
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/*
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* RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
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* (FreeRTOS Port)
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*
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* This header is the primary glue between generic Xtensa RTOS support
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* sources and a specific RTOS port for Xtensa. It contains definitions
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* and macros for use primarily by Xtensa assembly coded source files.
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*
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* Macros in this header map callouts from generic Xtensa files to specific
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* RTOS functions. It may also be included in C source files.
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*
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* Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
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* architecture, using the Xtensa hardware abstraction layer (HAL) to deal
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* with configuration specifics.
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*
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* Should be included by all Xtensa generic and RTOS port-specific sources.
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*/
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#ifndef XTENSA_RTOS_H
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#define XTENSA_RTOS_H
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@ -38,9 +36,9 @@ Should be included by all Xtensa generic and RTOS port-specific sources.
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/*
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Convert FreeRTOSConfig definitions to XTENSA definitions.
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However these can still be overridden from the command line.
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*/
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* Convert FreeRTOSConfig definitions to XTENSA definitions.
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* However these can still be overridden from the command line.
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*/
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#ifndef XT_SIMULATOR
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#if CONFIG_SIMULATOR_XTENSA
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@ -72,8 +70,8 @@ However these can still be overridden from the command line.
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/*
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Name of RTOS (for messages).
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*/
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* Name of RTOS (for messages).
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*/
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#define XT_RTOS_NAME Zephyr
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/*
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@ -83,104 +81,102 @@ Name of RTOS (for messages).
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#undef XT_RTOS_IS_FREE_RTOS
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/*
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Check some Xtensa configuration requirements and report error if not met.
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Error messages can be customize to the RTOS port.
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*/
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* Check some Xtensa configuration requirements and report error if not met.
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* Error messages can be customize to the RTOS port.
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*/
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#if !XCHAL_HAVE_XEA2
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#error "Zephyr/Xtensa requires XEA2 (exception architecture 2)."
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#endif
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/*******************************************************************************
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RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
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Define callout macros used in generic Xtensa code to interact with the RTOS.
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The macros are simply the function names for use in calls from assembler code.
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Some of these functions may call back to generic functions in xtensa_context.h .
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*******************************************************************************/
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/*
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* RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
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*
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* Define callout macros used in generic Xtensa code to interact with the RTOS.
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* The macros are simply the function names for use in calls from assembler
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* code.
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* Some of these functions may call back to generic functions in
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* xtensa_context.h .
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*/
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/*
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Inform RTOS of entry into an interrupt handler that will affect it.
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Allows RTOS to manage switch to any system stack and count nesting level.
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Called after minimal context has been saved, with interrupts disabled.
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RTOS port can call0 _xt_context_save to save the rest of the context.
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May only be called from assembly code by the 'call0' instruction.
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* Inform RTOS of entry into an interrupt handler that will affect it.
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* Allows RTOS to manage switch to any system stack and count nesting level.
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* Called after minimal context has been saved, with interrupts disabled.
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* RTOS port can call0 _xt_context_save to save the rest of the context.
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* May only be called from assembly code by the 'call0' instruction.
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*/
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// void XT_RTOS_INT_ENTER(void)
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#define XT_RTOS_INT_ENTER _zxt_int_enter
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/*
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Inform RTOS of completion of an interrupt handler, and give control to
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RTOS to perform thread/task scheduling, switch back from any system stack
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and restore the context, and return to the exit dispatcher saved in the
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stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
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to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
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leaving only a minimal part of the context to be restored by the exit
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dispatcher. This function does not return to the place it was called from.
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May only be called from assembly code by the 'call0' instruction.
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*/
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// void XT_RTOS_INT_EXIT(void)
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* Inform RTOS of completion of an interrupt handler, and give control to
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* RTOS to perform thread/task scheduling, switch back from any system stack
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* and restore the context, and return to the exit dispatcher saved in the
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* stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
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* to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
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* leaving only a minimal part of the context to be restored by the exit
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* dispatcher. This function does not return to the place it was called from.
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* May only be called from assembly code by the 'call0' instruction.
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*/
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#define XT_RTOS_INT_EXIT _zxt_int_exit
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/*
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Inform RTOS of the occurrence of a tick timer interrupt.
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If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
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May be coded in or called from C or assembly, per ABI conventions.
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RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
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*/
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// void XT_RTOS_TIMER_INT(void)
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* Inform RTOS of the occurrence of a tick timer interrupt.
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* If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
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* May be coded in or called from C or assembly, per ABI conventions.
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* RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
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*/
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#define XT_RTOS_TIMER_INT _zxt_timer_int
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#define XT_TICK_PER_SEC CONFIG_SYS_CLOCK_TICKS_PER_SEC
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/*
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Return in a15 the base address of the co-processor state save area for the
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thread that triggered a co-processor exception, or 0 if no thread was running.
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The state save area is structured as defined in xtensa_context.h and has size
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XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
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in interrupt handlers or the RTOS kernel. May only be called from assembly code
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and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
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The implementation may use only a2-4, a15 (all other regs must be preserved).
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*/
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// void* XT_RTOS_CP_STATE(void)
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* Return in a15 the base address of the co-processor state save area for the
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* thread that triggered a co-processor exception, or 0 if no thread was
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* running.
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* The state save area is structured as defined in xtensa_context.h and has size
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* XT_CP_SIZE. Co-processor instructions should only be used in thread code,
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* never in interrupt handlers or the RTOS kernel. May only be called from
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* assembly code and by the 'call0' instruction. A result of 0 indicates an
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* unrecoverable error.
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*
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* The implementation may use only a2-4, a15 (all other regs must be preserved).
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*/
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#define XT_RTOS_CP_STATE _zxt_task_coproc_state
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/*******************************************************************************
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HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
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This Xtensa RTOS port provides hooks for dynamically installing exception
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and interrupt handlers to facilitate automated testing where each test
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case can install its own handler for user exceptions and each interrupt
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priority (level). This consists of an array of function pointers indexed
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by interrupt priority, with index 0 being the user exception handler hook.
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Each entry in the array is initially 0, and may be replaced by a function
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pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
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The handler for low and medium priority obeys ABI conventions so may be coded
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in C. For the exception handler, the cause is the contents of the EXCCAUSE
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reg, and the result is -1 if handled, else the cause (still needs handling).
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For interrupt handlers, the cause is a mask of pending enabled interrupts at
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that level, and the result is the same mask with the bits for the handled
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interrupts cleared (those not cleared still need handling). This allows a test
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case to either pre-handle or override the default handling for the exception
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or interrupt level (see xtensa_vectors.S).
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High priority handlers (including NMI) must be coded in assembly, are always
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called by 'call0' regardless of ABI, must preserve all registers except a0,
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and must not use or modify the interrupted stack. The hook argument 'cause'
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is not passed and the result is ignored, so as not to burden the caller with
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saving and restoring a2 (it assumes only one interrupt per level - see the
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discussion in high priority interrupts in xtensa_vectors.S). The handler
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therefore should be coded to prototype 'void h(void)' even though it plugs
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into an array of handlers of prototype 'unsigned h(unsigned)'.
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To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
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*******************************************************************************/
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/*
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* HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
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*
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* This Xtensa RTOS port provides hooks for dynamically installing exception
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* and interrupt handlers to facilitate automated testing where each test
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* case can install its own handler for user exceptions and each interrupt
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* priority (level). This consists of an array of function pointers indexed
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* by interrupt priority, with index 0 being the user exception handler hook.
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* Each entry in the array is initially 0, and may be replaced by a function
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* pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
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*
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* The handler for low and medium priority obeys ABI conventions so may be coded
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* in C. For the exception handler, the cause is the contents of the EXCCAUSE
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* reg, and the result is -1 if handled, else the cause (still needs handling).
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* For interrupt handlers, the cause is a mask of pending enabled interrupts at
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* that level, and the result is the same mask with the bits for the handled
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* interrupts cleared (those not cleared still need handling). This allows a
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* test case to either pre-handle or override the default handling for the
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* exception or interrupt level (see xtensa_vectors.S).
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*
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* High priority handlers (including NMI) must be coded in assembly, are always
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* called by 'call0' regardless of ABI, must preserve all registers except a0,
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* and must not use or modify the interrupted stack. The hook argument 'cause'
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* is not passed and the result is ignored, so as not to burden the caller with
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* saving and restoring a2 (it assumes only one interrupt per level - see the
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* discussion in high priority interrupts in xtensa_vectors.S). The handler
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* therefore should be coded to prototype 'void h(void)' even though it plugs
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* into an array of handlers of prototype 'unsigned h(unsigned)'.
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*
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* To enable interrupt/exception hooks, compile the RTOS with
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* '-DXT_INTEXC_HOOKS'.
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*/
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#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
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#ifndef __ASSEMBLER__
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@ -189,14 +185,12 @@ extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
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#endif
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/*******************************************************************************
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CONVENIENCE INCLUSIONS.
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Ensures RTOS specific files need only include this one Xtensa-generic header.
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These headers are included last so they can use the RTOS definitions above.
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*******************************************************************************/
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/*
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* CONVENIENCE INCLUSIONS.
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*
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* Ensures RTOS specific files need only include this one Xtensa-generic header.
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* These headers are included last so they can use the RTOS definitions above.
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*/
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#include "xtensa_context.h"
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@ -204,14 +198,4 @@ These headers are included last so they can use the RTOS definitions above.
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#include "xtensa_timer.h"
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#endif
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/*******************************************************************************
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Xtensa Port Version.
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*******************************************************************************/
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#define XTENSA_PORT_VERSION 1.5.0
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#define XTENSA_PORT_VERSION_STRING "1.5.0"
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#endif /* XTENSA_RTOS_H */
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@ -3,23 +3,21 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
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This header contains definitions and macros for use primarily by Xtensa
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RTOS assembly coded source files. It includes and uses the Xtensa hardware
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abstraction layer (HAL) to deal with config specifics. It may also be
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included in C source files.
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User may edit to modify timer selection and to specify clock frequency and
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tick duration to match timer interrupt to the real-time tick duration.
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If the RTOS has no timer interrupt, then there is no tick timer and the
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clock frequency is irrelevant, so all of these macros are left undefined
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and the Xtensa core configuration need not have a timer.
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*******************************************************************************/
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/*
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* XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
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*
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* This header contains definitions and macros for use primarily by Xtensa
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* RTOS assembly coded source files. It includes and uses the Xtensa hardware
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* abstraction layer (HAL) to deal with config specifics. It may also be
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* included in C source files.
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*
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* User may edit to modify timer selection and to specify clock frequency and
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* tick duration to match timer interrupt to the real-time tick duration.
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*
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* If the RTOS has no timer interrupt, then there is no tick timer and the
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* clock frequency is irrelevant, so all of these macros are left undefined
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* and the Xtensa core configuration need not have a timer.
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*/
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#ifndef XTENSA_TIMER_H
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#define XTENSA_TIMER_H
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@ -35,52 +33,50 @@ and the Xtensa core configuration need not have a timer.
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#if CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0)
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/*
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Select timer to use for periodic tick, and determine its interrupt number
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and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
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in which case its validity is checked (it must exist in this core and must
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not be on a high priority interrupt - an error will be reported in invalid).
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Otherwise select the first low or medium priority interrupt timer available.
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*/
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* Select timer to use for periodic tick, and determine its interrupt number
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* and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
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* in which case its validity is checked (it must exist in this core and must
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* not be on a high priority interrupt - an error will be reported in invalid).
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* Otherwise select the first low or medium priority interrupt timer available.
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*/
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#if XCHAL_NUM_TIMERS == 0
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#error "This Xtensa configuration is unsupported, it has no timers."
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#error "This Xtensa configuration is unsupported, it has no timers."
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#endif /* XCHAL_NUM_TIMERS */
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#ifndef XT_TIMER_INDEX
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#if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 3
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#endif
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#endif
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#if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 2
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#endif
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#endif
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#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 1
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#endif
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#endif
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#if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 0
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#endif
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#endif
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#if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 3
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#endif
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#endif
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#if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 2
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#endif
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#endif
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#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 1
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#endif
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#endif
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#if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 0
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#endif
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#endif
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#endif
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#ifndef XT_TIMER_INDEX
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#error "There is no suitable timer in this Xtensa configuration."
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#error "There is no suitable timer in this Xtensa configuration."
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#endif
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#define XT_CCOMPARE ((CCOMPARE) + (XT_TIMER_INDEX))
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#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
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#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
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#error "The timer selected by XT_TIMER_INDEX does not exist in this core."
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#error "The timer selected by XT_TIMER_INDEX does not exist in this core."
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#endif
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#else /* Case of an external timer which is not emulated by internal timer */
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#define XT_TIMER_INTNUM CONFIG_XTENSA_TIMER_IRQ
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|
|
@ -93,50 +89,53 @@ Otherwise select the first low or medium priority interrupt timer available.
|
|||
#endif /* CONFIG_XTENSA_INTERNAL_TIMER */
|
||||
|
||||
#if XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
|
||||
#error "The timer interrupt cannot be high priority (use medium or low)."
|
||||
#error "The timer interrupt cannot be high priority (use medium or low)."
|
||||
#endif
|
||||
|
||||
#define XT_TIMER_INTEN (1 << (XT_TIMER_INTNUM))
|
||||
|
||||
/*
|
||||
Set processor clock frequency, used to determine clock divisor for timer tick.
|
||||
User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
|
||||
If using a supported board via the board-independent API defined in xtbsp.h,
|
||||
this may be left undefined and frequency and tick divisor will be computed
|
||||
and cached during run-time initialization.
|
||||
|
||||
NOTE ON SIMULATOR:
|
||||
Under the Xtensa instruction set simulator, the frequency can only be estimated
|
||||
because it depends on the speed of the host and the version of the simulator.
|
||||
Also because it runs much slower than hardware, it is not possible to achieve
|
||||
real-time performance for most applications under the simulator. A frequency
|
||||
too low does not allow enough time between timer interrupts, starving threads.
|
||||
To obtain a more convenient but non-real-time tick duration on the simulator,
|
||||
compile with xt-xcc option "-DXT_SIMULATOR".
|
||||
Adjust this frequency to taste (it's not real-time anyway!).
|
||||
*/
|
||||
* Set processor clock frequency, used to determine clock divisor for timer
|
||||
* tick.
|
||||
* User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
|
||||
* If using a supported board via the board-independent API defined in xtbsp.h,
|
||||
* this may be left undefined and frequency and tick divisor will be computed
|
||||
* and cached during run-time initialization.
|
||||
*
|
||||
* NOTE ON SIMULATOR:
|
||||
* Under the Xtensa instruction set simulator, the frequency can only be
|
||||
* estimated
|
||||
* because it depends on the speed of the host and the version of the simulator.
|
||||
* Also because it runs much slower than hardware, it is not possible to achieve
|
||||
* real-time performance for most applications under the simulator. A frequency
|
||||
* too low does not allow enough time between timer interrupts, starving
|
||||
* threads.
|
||||
* To obtain a more convenient but non-real-time tick duration on the simulator,
|
||||
* compile with xt-xcc option "-DXT_SIMULATOR".
|
||||
* Adjust this frequency to taste (it's not real-time anyway!).
|
||||
*/
|
||||
#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
|
||||
#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
#endif
|
||||
|
||||
#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
|
||||
#error "XT_CLOCK_FREQ must be defined for the target platform."
|
||||
#error "XT_CLOCK_FREQ must be defined for the target platform."
|
||||
#endif
|
||||
|
||||
/*
|
||||
Default number of timer "ticks" per second (default 100 for 10ms tick).
|
||||
RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
|
||||
User may redefine this to an optimal value for the application, either by
|
||||
editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
|
||||
"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
|
||||
*/
|
||||
* Default number of timer "ticks" per second (default 100 for 10ms tick).
|
||||
* RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
|
||||
* User may redefine this to an optimal value for the application, either by
|
||||
* editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
|
||||
* "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
|
||||
*/
|
||||
#ifndef XT_TICK_PER_SEC
|
||||
#define XT_TICK_PER_SEC CONFIG_SYS_CLOCK_TICKS_PER_SEC /* 10 ms tick = 100 ticks per second */
|
||||
#define XT_TICK_PER_SEC CONFIG_SYS_CLOCK_TICKS_PER_SEC
|
||||
#endif
|
||||
|
||||
/*
|
||||
Derivation of clock divisor for timer tick and interrupt (one per tick).
|
||||
*/
|
||||
* Derivation of clock divisor for timer tick and interrupt (one per tick).
|
||||
*/
|
||||
#ifdef XT_CLOCK_FREQ
|
||||
#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue