llext: add support for arc

Adds compiler flag(s) and some architecture-specific relocations
for ARC. No userspace support, doesn't support all relocations.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
This commit is contained in:
Lauren Murphy 2024-09-11 14:26:22 -07:00 committed by Anas Nashif
commit 99a5236b40
8 changed files with 137 additions and 11 deletions

View file

@ -34,3 +34,5 @@ add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield)
zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)
zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)

79
arch/arc/core/elf.c Normal file
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@ -0,0 +1,79 @@
/*
* Copyright (c) 2024 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/llext/elf.h>
#include <zephyr/llext/llext.h>
#include <zephyr/llext/loader.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL);
#define R_ARC_32 4
#define R_ARC_B26 5 /* AKA R_ARC_64 */
#define R_ARC_S25W_PCREL 17
#define R_ARC_32_ME 27
/* ARCompact insns packed in memory have Middle Endian encoding */
#define ME(x) ((x & 0xffff0000) >> 16) | ((x & 0xffff) << 16);
/**
* @brief Architecture specific function for relocating shared elf
*
* Elf files contain a series of relocations described in multiple sections.
* These relocation instructions are architecture specific and each architecture
* supporting modules must implement this.
*
* The relocation codes are well documented:
* https://github.com/foss-for-synopsys-dwc-arc-processors/arc-ABI-manual/blob/master/ARCv2_ABI.pdf
* https://github.com/zephyrproject-rtos/binutils-gdb
*/
int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name,
uintptr_t load_bias)
{
int ret = 0;
uint32_t insn = *(uint32_t *)loc;
uint32_t value;
sym_base_addr += rel->r_addend;
int reloc_type = ELF32_R_TYPE(rel->r_info);
switch (reloc_type) {
case R_ARC_32:
case R_ARC_B26:
*(uint32_t *)loc = sym_base_addr;
break;
case R_ARC_S25W_PCREL:
/* ((S + A) - P) >> 2
* S = symbol address
* A = addend
* P = relative offset to PCL
*/
value = (sym_base_addr + rel->r_addend - (loc & ~0x3)) >> 2;
insn = ME(insn);
/* disp25w */
insn = insn & ~0x7fcffcf;
insn |= ((value >> 0) & 0x01ff) << 18;
insn |= ((value >> 9) & 0x03ff) << 6;
insn |= ((value >> 19) & 0x000f) << 0;
insn = ME(insn);
*(uint32_t *)loc = insn;
break;
case R_ARC_32_ME:
*(uint32_t *)loc = ME(sym_base_addr);
break;
default:
LOG_ERR("unknown relocation: %u\n", reloc_type);
ret = -ENOEXEC;
break;
}
return ret;
}

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@ -8,5 +8,16 @@ if(NOT DEFINED GCC_ARC_TUNED_CPU)
set(GCC_ARC_TUNED_CPU ${GCC_M_CPU})
endif()
# Flags not supported by llext linker
# (regexps are supported and match whole word)
set(LLEXT_REMOVE_FLAGS
-fno-pic
-fno-pie
-ffunction-sections
-fdata-sections
-g.*
-Os
)
list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_ARC_TUNED_CPU})
list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_ARC_TUNED_CPU})

View file

@ -21,4 +21,4 @@ and introspected to some degree, as well as unloaded when no longer needed.
.. note::
The LLEXT subsystem requires architecture-specific support. It is currently
available only on RISC-V, ARM, ARM64 and Xtensa cores.
available only on RISC-V, ARM, ARM64, ARC (experimental) and Xtensa cores.

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@ -0,0 +1,6 @@
CONFIG_FILE_SYSTEM=y
CONFIG_FILE_SYSTEM_LITTLEFS=y
CONFIG_FS_LITTLEFS_FMP_DEV=y
CONFIG_FLASH_MAP=y
CONFIG_FLASH=y
CONFIG_FLASH_SIMULATOR=y

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@ -0,0 +1,28 @@
/ {
sim_flash_controller: sim_flash_controller {
compatible = "zephyr,sim-flash";
#address-cells = <1>;
#size-cells = <1>;
erase-value = <0x00>;
flash_sim0: flash_sim@0 {
compatible = "soc-nv-flash";
reg = <0x00000000 0x2000>;
erase-block-size = <1024>;
write-block-size = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage_partition";
reg = <0x00000000 0x2000>;
};
};
};
};
};

View file

@ -6,3 +6,4 @@
CONFIG_ARM_MPU=n
CONFIG_ARM_AARCH32_MMU=n
CONFIG_RISCV_PMP=n
CONFIG_ARC_MPU_ENABLE=n

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@ -6,11 +6,6 @@ common:
- s32z2xxdc2/s32z270/rtu0 # See commit 18a0660
- s32z2xxdc2/s32z270/rtu1 # See commit 18a0660
# platforms that are always skipped by the runtime filter
- qemu_arc/qemu_arc_em
- qemu_arc/qemu_arc_hs
- qemu_arc/qemu_arc_hs/xip
- qemu_arc/qemu_arc_hs5x
- qemu_arc/qemu_arc_hs6x
- qemu_cortex_m0
- qemu_xtensa/dc233c/mmu
integration_platforms:
@ -36,7 +31,7 @@ tests:
# most tests include no_mem_protection.conf, which disables memory protection
# hardware completely.
llext.simple.readonly:
arch_allow: arm riscv # Xtensa needs writable storage
arch_allow: arm riscv arc # Xtensa needs writable storage
filter: not CONFIG_MPU and not CONFIG_MMU
extra_conf_files: ['no_mem_protection.conf']
extra_configs:
@ -57,7 +52,7 @@ tests:
- CONFIG_LLEXT_HEAP_SIZE=128 # qemu_cortex_a9 requires larger heap
- CONFIG_LLEXT_STORAGE_WRITABLE=n
llext.simple.writable:
arch_allow: arm xtensa riscv
arch_allow: arm xtensa riscv arc
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
@ -65,7 +60,9 @@ tests:
extra_configs:
- CONFIG_LLEXT_STORAGE_WRITABLE=y
llext.simple.writable_relocatable:
arch_allow: arm xtensa riscv
arch_allow: arm xtensa riscv arc
platform_exclude:
- qemu_arc/qemu_arc_hs5x # See #80949
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
@ -77,7 +74,7 @@ tests:
# Test the Symbol Link Identifier (SLID) linking feature on writable
# storage to cover both ARM and Xtensa architectures on the same test.
llext.simple.writable_slid_linking:
arch_allow: arm xtensa riscv
arch_allow: arm xtensa riscv arc
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
@ -86,7 +83,9 @@ tests:
- CONFIG_LLEXT_STORAGE_WRITABLE=y
- CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID=y
llext.simple.writable_relocatable_slid_linking:
arch_allow: arm xtensa riscv
arch_allow: arm xtensa riscv arc
platform_exclude:
- qemu_arc/qemu_arc_hs5x # See #80949
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU