llext: add support for arc
Adds compiler flag(s) and some architecture-specific relocations for ARC. No userspace support, doesn't support all relocations. Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
This commit is contained in:
Lauren Murphy
Anas Nashif
parent
18853d026a
commit
99a5236b40
8 changed files with 137 additions and 11 deletions
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@ -34,3 +34,5 @@ add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
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add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield)
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zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)
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zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)
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79
arch/arc/core/elf.c
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79
arch/arc/core/elf.c
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@ -0,0 +1,79 @@
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/*
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* Copyright (c) 2024 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/llext/elf.h>
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#include <zephyr/llext/llext.h>
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#include <zephyr/llext/loader.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL);
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#define R_ARC_32 4
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#define R_ARC_B26 5 /* AKA R_ARC_64 */
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#define R_ARC_S25W_PCREL 17
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#define R_ARC_32_ME 27
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/* ARCompact insns packed in memory have Middle Endian encoding */
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#define ME(x) ((x & 0xffff0000) >> 16) | ((x & 0xffff) << 16);
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/**
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* @brief Architecture specific function for relocating shared elf
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*
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* Elf files contain a series of relocations described in multiple sections.
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* These relocation instructions are architecture specific and each architecture
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* supporting modules must implement this.
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*
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* The relocation codes are well documented:
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* https://github.com/foss-for-synopsys-dwc-arc-processors/arc-ABI-manual/blob/master/ARCv2_ABI.pdf
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* https://github.com/zephyrproject-rtos/binutils-gdb
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*/
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int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name,
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uintptr_t load_bias)
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{
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int ret = 0;
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uint32_t insn = *(uint32_t *)loc;
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uint32_t value;
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sym_base_addr += rel->r_addend;
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int reloc_type = ELF32_R_TYPE(rel->r_info);
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switch (reloc_type) {
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case R_ARC_32:
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case R_ARC_B26:
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*(uint32_t *)loc = sym_base_addr;
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break;
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case R_ARC_S25W_PCREL:
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/* ((S + A) - P) >> 2
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* S = symbol address
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* A = addend
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* P = relative offset to PCL
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*/
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value = (sym_base_addr + rel->r_addend - (loc & ~0x3)) >> 2;
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insn = ME(insn);
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/* disp25w */
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insn = insn & ~0x7fcffcf;
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insn |= ((value >> 0) & 0x01ff) << 18;
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insn |= ((value >> 9) & 0x03ff) << 6;
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insn |= ((value >> 19) & 0x000f) << 0;
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insn = ME(insn);
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*(uint32_t *)loc = insn;
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break;
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case R_ARC_32_ME:
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*(uint32_t *)loc = ME(sym_base_addr);
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break;
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default:
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LOG_ERR("unknown relocation: %u\n", reloc_type);
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ret = -ENOEXEC;
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break;
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}
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return ret;
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}
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@ -8,5 +8,16 @@ if(NOT DEFINED GCC_ARC_TUNED_CPU)
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set(GCC_ARC_TUNED_CPU ${GCC_M_CPU})
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endif()
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# Flags not supported by llext linker
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# (regexps are supported and match whole word)
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set(LLEXT_REMOVE_FLAGS
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-fno-pic
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-fno-pie
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-ffunction-sections
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-fdata-sections
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-g.*
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-Os
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)
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list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_ARC_TUNED_CPU})
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list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_ARC_TUNED_CPU})
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@ -21,4 +21,4 @@ and introspected to some degree, as well as unloaded when no longer needed.
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.. note::
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The LLEXT subsystem requires architecture-specific support. It is currently
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available only on RISC-V, ARM, ARM64 and Xtensa cores.
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available only on RISC-V, ARM, ARM64, ARC (experimental) and Xtensa cores.
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@ -0,0 +1,6 @@
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CONFIG_FILE_SYSTEM=y
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CONFIG_FILE_SYSTEM_LITTLEFS=y
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CONFIG_FS_LITTLEFS_FMP_DEV=y
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CONFIG_FLASH_MAP=y
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CONFIG_FLASH=y
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CONFIG_FLASH_SIMULATOR=y
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@ -0,0 +1,28 @@
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/ {
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sim_flash_controller: sim_flash_controller {
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compatible = "zephyr,sim-flash";
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#address-cells = <1>;
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#size-cells = <1>;
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erase-value = <0x00>;
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flash_sim0: flash_sim@0 {
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compatible = "soc-nv-flash";
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reg = <0x00000000 0x2000>;
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erase-block-size = <1024>;
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write-block-size = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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storage_partition: partition@0 {
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label = "storage_partition";
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reg = <0x00000000 0x2000>;
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};
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};
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};
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};
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};
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@ -6,3 +6,4 @@
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CONFIG_ARM_MPU=n
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CONFIG_ARM_AARCH32_MMU=n
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CONFIG_RISCV_PMP=n
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CONFIG_ARC_MPU_ENABLE=n
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@ -6,11 +6,6 @@ common:
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- s32z2xxdc2/s32z270/rtu0 # See commit 18a0660
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- s32z2xxdc2/s32z270/rtu1 # See commit 18a0660
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# platforms that are always skipped by the runtime filter
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- qemu_arc/qemu_arc_em
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- qemu_arc/qemu_arc_hs
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- qemu_arc/qemu_arc_hs/xip
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- qemu_arc/qemu_arc_hs5x
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- qemu_arc/qemu_arc_hs6x
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- qemu_cortex_m0
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- qemu_xtensa/dc233c/mmu
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integration_platforms:
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@ -36,7 +31,7 @@ tests:
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# most tests include no_mem_protection.conf, which disables memory protection
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# hardware completely.
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llext.simple.readonly:
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arch_allow: arm riscv # Xtensa needs writable storage
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arch_allow: arm riscv arc # Xtensa needs writable storage
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filter: not CONFIG_MPU and not CONFIG_MMU
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extra_conf_files: ['no_mem_protection.conf']
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extra_configs:
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@ -57,7 +52,7 @@ tests:
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- CONFIG_LLEXT_HEAP_SIZE=128 # qemu_cortex_a9 requires larger heap
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- CONFIG_LLEXT_STORAGE_WRITABLE=n
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llext.simple.writable:
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arch_allow: arm xtensa riscv
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arch_allow: arm xtensa riscv arc
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integration_platforms:
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- qemu_xtensa/dc233c # Xtensa ISA
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filter: not CONFIG_MPU and not CONFIG_MMU
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@ -65,7 +60,9 @@ tests:
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extra_configs:
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- CONFIG_LLEXT_STORAGE_WRITABLE=y
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llext.simple.writable_relocatable:
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arch_allow: arm xtensa riscv
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arch_allow: arm xtensa riscv arc
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platform_exclude:
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- qemu_arc/qemu_arc_hs5x # See #80949
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integration_platforms:
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- qemu_xtensa/dc233c # Xtensa ISA
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filter: not CONFIG_MPU and not CONFIG_MMU
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@ -77,7 +74,7 @@ tests:
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# Test the Symbol Link Identifier (SLID) linking feature on writable
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# storage to cover both ARM and Xtensa architectures on the same test.
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llext.simple.writable_slid_linking:
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arch_allow: arm xtensa riscv
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arch_allow: arm xtensa riscv arc
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integration_platforms:
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- qemu_xtensa/dc233c # Xtensa ISA
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filter: not CONFIG_MPU and not CONFIG_MMU
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@ -86,7 +83,9 @@ tests:
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- CONFIG_LLEXT_STORAGE_WRITABLE=y
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- CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID=y
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llext.simple.writable_relocatable_slid_linking:
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arch_allow: arm xtensa riscv
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arch_allow: arm xtensa riscv arc
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platform_exclude:
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- qemu_arc/qemu_arc_hs5x # See #80949
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integration_platforms:
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- qemu_xtensa/dc233c # Xtensa ISA
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filter: not CONFIG_MPU and not CONFIG_MMU
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