Introduce `z_riscv_pmp_write_config` to abstract writing to pmpcfg
registers. This function handles the differing register layouts and slot
counts between RV32 and RV64 architectures, writing to the appropriate
pmpcfg0, pmpcfg1, pmpcfg2, or pmpcfg3 CSRs as needed based on
CONFIG_PMP_SLOTS.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Move Xuantie supprot from arch/riscv/core/xuantie to the custom common
layer arch/riscv/custom/thead, with the following changes:
1. Rename Kconfig name
CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO
2. Split the original arch/riscv/core/xuantie/Kconfig to
a. arch/riscv/custom/thead/Kconfig: for T-Head extension
b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series
(e.g. Xuantie E907)
3. Move cache line size defaults to SoC devicetree
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Update OpenISA RI5CY and Zero-RISCY CSR handling to use RISC-V custom
CSR common code. Move these stuff to 'arch/riscv/custom/openisa':
1. Rename 'soc_ri5cy.h' to 'ri5cy_csr.h' for CSR definitions.
2. Rename 'soc_zero_riscy.h' to 'zero_riscy_csr.h' for CSR definitions.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move compiler option '-march=rv32imcxpulpv2' to common code.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h',
allowing other SoCs using the CVA6 core to reuse the same CSR definitions.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to
'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Rework Andes-specific CSR to use RISC-V custom CSR common code.
Move these stuff to 'arch/riscv/custom/andes':
1. Rename 'soc_v5.h' to 'andes_csr.h' for CSR definitions.
2. Replace '_start' with '__reset' hook for low-level CSR initialization.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move 'EXECIT' CSR support to common code.
5. Move PMA CSR driver to common code.
6. Use RISC-V common linker.ld instead of SoC-specific linker.ld.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
RISC-V allows custom CSR implementation. Some SoCs from different vendors
may share the same core or the same custom CSR definitions and drivers.
This patch introduces 'arch/riscv/custom', which centralizes support
for custom CSRs, allowing code reuse across SoCs that come from different
vendors. Currently supported thess custom CSR:
1. Andes
2. Nuclei
3. OpenHWGroup CVA6
4. OpenISA RI5CY
5. OpenISA Zero-riscy
6. T-Head Xuantie
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The PMP initialization and thread seeding logic in arch/riscv/core/pmp.c
did not correctly handle scenarios where the global PMP entries span
across multiple `pmpcfg` hardware registers.
The `global_pmp_cfg` array, intended to store the hardware register
values, was hardcoded to size 1. This is only sufficient if all global
PMP entries fall within the range covered by the first `pmpcfg` register
(e.g., pmpcfg0). When more global entries are used, their configurations
reside in subsequent `pmpcfg` registers (pmpcfg1, pmpcfg2, etc.).
The code was only saving/restoring and checking `global_pmp_cfg[0]`,
leading to loss of configuration for entries mapped to higher `pmpcfg`
registers.
This patch fixes this by:
1. Resizing the `global_pmp_cfg` array to
`CONFIG_PMP_SLOTS / PMPCFG_STRIDE` to correctly accommodate values
from all potentially used `pmpcfg` CSRs.
2. In `z_riscv_pmp_init`, using `memcpy` to save the entire contents of
the local `pmp_cfg` array (derived from initial setup) into the
`global_pmp_cfg` array.
3. In `z_riscv_pmp_thread_init`, using `memcpy` to restore the entire
saved global configuration from `global_pmp_cfg` into a thread's
`pmp_cfg` array.
4. Updating the SMP consistency assertion in `z_riscv_pmp_init` to
compare the contents of the array element @ `index / PMPCFG_STRIDE`
of the `pmp_cfg` arrays.
These changes ensure that the configurations from all relevant `pmpcfg`
registers are preserved and correctly propagated to thread contexts.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Factor out the logic for reading PMP configuration registers (pmpcfgX)
from dump_pmp_regs into a new static inline helper function,
z_riscv_pmp_read_config.
This new function encapsulates the architecture-specific (RV32/RV64)
and slot-count-specific reads of the pmpcfg CSRs, improving code
organization and potential reusability.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
The arrays used for M-mode Physical Memory Protection (PMP),
specifically for the stack guard feature (CONFIG_PMP_STACK_GUARD),
were previously sized using the hardcoded PMP_M_MODE_SLOTS macro,
defined as 8. This affected arrays in both the _thread_arch
struct (m_mode_pmpaddr_regs, m_mode_pmpcfg_regs) and local
variables within the z_riscv_pmp_stackguard_disable function.
This commit changes the array sizing to use the Kconfig option
CONFIG_PMP_SLOTS. This option reflects the total number of PMP
slots available and configured for the target hardware.
Using CONFIG_PMP_SLOTS ensures these arrays are dimensioned
according to the system's actual capabilities, providing better
flexibility and correctness over a fixed size.
The PMP_M_MODE_SLOTS macro definition has been removed from
thread.h as it is no longer used.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Do not directly include and use APIs from ksched.h outside of the
kernel. For now do this using more suitable (ipi.h and
kernel_internal.h) internal APIs until more cleanup is done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
z_prep_c does not return, mark it as such consistently across
architectures. We had some arches do that, others not. This resolves a
few coding guideline violations in arch code.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup init.c code and move early boot code into arch/ and make it
accessible outside of the boot process/kernel.
All of this code is not related to the 'kernel' and is mostly used
within the architecture boot / setup process.
The way it was done, some soc code was including kernel_internal.h
directly, which shouldn't be done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Not really a kernel feature, more for architecture, which is reflected
in how XIP is enabled and tested. Move it to architecture code to keep
which much of the 'implementation' and usage is.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added helper Kcoinfig option USE_ISR_WRAPPER which can be used to
include isr_wrapper even if GEN_SW_ISR_TABLE is not enabled. This
is needed to enable configurations where only IRQ vector table is
used with multithreading (only direct isr used). This change is
backward compatibible with previous config.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
Introduce CONFIG_RISCV_NO_MTVAL_ON_FP_TRAP to handle implementations
where the mtval CSR does not provide useful information during
floating-point illegal instruction exceptions.
The RISC-V specification states that mtval is "either set to zero or
written with exception-specific information" on traps. Some
implementations, including QEMU, do not populate mtval with the
faulting instruction value during FP-related illegal instruction
exceptions, making it unusable for FP exception handling.
Previously, this behavior was hardcoded for QEMU targets only, but
other CPU implementations may also lack useful mtval content for FP
traps. Decoupling this from CONFIG_QEMU_TARGET and allows other
platforms to properly declare this limitation.
The new Kconfig option defaults to enabled for QEMU targets to
maintain backward compatibility.
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
The intent of arch_coprocessors_disable() is to replace
arch_float_disable() in halt_thread() for the FPU will not
always be the only coprocessor that will need to be disabled.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit introduces a new Kconfig choice for configuring the code model
used for compilation.
All three code models specified by the RISC-V ELF psABI specification are
supported: medlow, medany and large.
For RV32, the `medlow` code model is always selected.
For RV64, the `large` code model is selected if the SRAM or kernel VM base
address is greater than or equal to 4 GiB; otherwise, the `medany` code
model is selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit introduces the support for the standard Zicntr extension, which
provides hardware counters.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the support for the following new Zc* series compressed
instruction extensions:
Zca - Subset of the C extension without FP loads and stores
Zcb - "Simple" instructions
Zcd - Double-precision floating-point instructions
Zcf - Single-precision floating-point instructions
Zcmp - "Complex" instructions for embedded CPUs
Zcmt - Table jump instructions for embedded CPUs
With the introduction of the Zc* extensions, the C extension now implies
the following Zc* extensions:
* Zca, always
* Zcf if F is specified (RV32 only)
* Zcd if D is specified
The Zc* extensions that are implied by the C extension are not specified in
the GCC `-march` flag because they are redundant and can interfere with the
resolution of the correct multi-lib for the selected architecture unless
the the alternate mappings for the redundant forms are manually specified.
All the implementation details in this commit are based on the Zc* v1.0.0
specification, which is the ratified version.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `arch`, `boards`, `kernel`, `modules`,
`samples`, and `share` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
riscv_cpu_wake_flag and riscv_cpu_sp are variables, not functions, so
they should use the GDATA macro instead of the GTEXT macro. Otherwise,
the linker will warn when LTO is enabled:
ld.bfd: warning: type of symbol `riscv_cpu_wake_flag' changed from 2 to
1 in /tmp/cc39w5oK.ltrans0.ltrans.o
ld.bfd: warning: type of symbol `riscv_cpu_sp' changed from 2 to 1 in
/tmp/cc39w5oK.ltrans0.ltrans.o
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Initializing the C++ stack unwinding data structures takes quite a bit
of stack space. Increase the TEST_EXTRA_STACK_SIZE when using these.
Signed-off-by: Keith Packard <keithp@keithp.com>
The QingKe V2C has an integer multiplier but no divide. Add support
for the corresponding Zmmul extension and, as the extension was added
in GCC 13.0, add a test for the compiler version.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The declaration for the text region '__text_region_start' and
'__text_region_end' should be consistent with the declaration in the
include file 'zephyr/linker/linker-defs.h'.
The local declarations are:
extern uintptr_t __text_region_start, __text_region_end;
whereas 'linker_defs.h' declares them as:
extern char __text_region_start[];
extern char __text_region_end[];
This may result in conflicting types when 'linker_defs.h' is indirectly
included. Hence, remove the local declarations.
Signed-off-by: Christoph Winklhofer <cj.winklhofer@gmail.com>
Add sys_trace_idle_exit to RISCV cpu_idle functions and allow
enabling CPU_LOAD module for RISCV and disable it for SMP.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Since 3466dab804 the generic llext_symbol_name() function abstracts
the use of llext_string() for (non-section) symbols. Define a similar
llext_section_name() function and replace current occurrences of
llext_string() with the proper abstraction.
By extending llext_symbol_name(), this commit also allows to print the
correct name of sections that are referred to by a symbol.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Currently, RISC-V's architecture-specific relocations assume that
all relocations of type R_RISCV_PCREL_LO12_I and _S are processed
immediately after the R_RISCV_PCREL_HI20 relocation that they
share a relocation target with. While this is the case most of
the time, the RISC-V PSABI specification does not guarantee that.
This commit corrects this by determining the R_RISCV_PCREL_HI20
relocation based on the symbol value of the R_RISCV_PCREL_LO12
relocation, as specified in the PSABI.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The RISC-V port of llext requires additional parameters for
handling non-adjacent HI20/LO12 relocations in arch_elf_relocate():
the current extension (struct llext), the current extension loader
(struct llext_loader), the current section header (elf_shdr_t) and
the current symbol (elf_sym_t).
This changes the signature of arch_elf_relocate accordingly.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The Zaamo and Zalrsc Extension (Version v1.0.0, 2024-04-25; Ratified) split
the standard A extension into two subextensions. As of date, the `_zaamo`
and `_zlrsc` extension specifications are accepted by the upstream
in-development GCC through the `march` argument. This means that those
subextensions are not yet supported by GCC shipped with Zephyr SDK.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
CLIC supports mintstatus.MIL (RO) and mcause.MPIL (RW) for the current
interrupt level and the previous interrut level before a trap. Each ISR
must execute MRET to set mcause.MPIL back to mintstatus.MIL.
This commit introduces CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL to handle
mcause.MPIL for interrupt preemption in nested ISR, and uses
CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL to ensure ISR always switch out
with MRET.
e.g.
With CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL=n, a context-switch in
ISR may skip MRET in this flow:
IRQ -> _isr_wrapper -> z_riscv_switch() -> retrun to arch_switch()
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The exception fault handler function is named _Fault which is inconsistent
with all other arch-specific functions present in Zephyr. This patch
replaces the name with z_riscv_fault.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
When RISCV_SOC_HAS_ISR_STACKING is used, it may
be needed to initialize custom hw stacked esf members.
Some initial values may need to be aligned with
hw stacking mechanism to avoid any side effects.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
The RISC-V architecture-specific relocations need to check whether
each required relocation can fit into the modified instruction's
immediate. All immediates in RISC-V are encoded as two's complement.
The current truncation check has an off-by-one error for checking
the maximum negative distance, as two's complement encoding can
represent a negative value that is the maximum positive value plus
one, causing LLEXT to refuse loading valid code.
This commit adds an additional condition to the check that fixes
the aforementioned issue.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Mostly a revert of commit b1def7145f ("arch: deprecate `_current`").
This commit was part of PR #80716 whose initial purpose was about providing
an architecture specific optimization for _current. The actual deprecation
was sneaked in later on without proper discussion.
The Zephyr core always used _current before and that was fine. It is quite
prevalent as well and the alternative is proving rather verbose.
Furthermore, as a concept, the "current thread" is not something that is
necessarily architecture specific. Therefore the primary abstraction
should not carry the arch_ prefix.
Hence this revert.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.
To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.
`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Reset the the `gp` register to `_kernel->cpus[i].current` when
`CONFIG_USERSPACE` is enabled on exception to keep it sane.
Updated the testcase to test both `CONFIG_RISCV_GP` and
`CONFIG_RISCV_CURRENT_VIA_GP`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
In most implements, the msip base address is 0x2000000. But the address
is not fixed in all boards.
Signed-off-by: Yang Jialong <yangjialong@vcore.com>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Implement `arch_curr_thread()` & `arch_set_curr_thread()`
with the global pointer (GP) register.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
