arch: riscv: fatal: always print mcause & mtval
Relocate the logging of mcause & mtval from `_Fault` to `z_riscv_fatal_error_csf` so that they are always printed upon exception. Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
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1 changed files with 51 additions and 52 deletions
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@ -52,6 +52,42 @@ uintptr_t z_riscv_get_sp_before_exc(const struct arch_esf *esf)
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return sp;
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}
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static char *cause_str(unsigned long cause)
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{
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switch (cause) {
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case 0:
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return "Instruction address misaligned";
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case 1:
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return "Instruction Access fault";
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case 2:
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return "Illegal instruction";
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case 3:
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return "Breakpoint";
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case 4:
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return "Load address misaligned";
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case 5:
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return "Load access fault";
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case 6:
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return "Store/AMO address misaligned";
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case 7:
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return "Store/AMO access fault";
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case 8:
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return "Environment call from U-mode";
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case 9:
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return "Environment call from S-mode";
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case 11:
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return "Environment call from M-mode";
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case 12:
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return "Instruction page fault";
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case 13:
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return "Load page fault";
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case 15:
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return "Store/AMO page fault";
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default:
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return "unknown";
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}
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}
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FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
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const struct arch_esf *esf)
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{
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@ -61,6 +97,21 @@ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
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FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const struct arch_esf *esf,
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const _callee_saved_t *csf)
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{
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unsigned long mcause;
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__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
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mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK;
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LOG_ERR("");
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LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
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#ifndef CONFIG_SOC_OPENISA_RV32M1
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unsigned long mtval;
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__asm__ volatile("csrr %0, mtval" : "=r" (mtval));
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LOG_ERR(" mtval: %lx", mtval);
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#endif /* CONFIG_SOC_OPENISA_RV32M1 */
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#ifdef CONFIG_EXCEPTION_DEBUG
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if (esf != NULL) {
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LOG_ERR(" a0: " PR_REG " t0: " PR_REG, esf->a0, esf->t0);
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@ -108,42 +159,6 @@ FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const struct arc
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CODE_UNREACHABLE;
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}
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static char *cause_str(unsigned long cause)
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{
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switch (cause) {
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case 0:
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return "Instruction address misaligned";
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case 1:
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return "Instruction Access fault";
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case 2:
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return "Illegal instruction";
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case 3:
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return "Breakpoint";
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case 4:
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return "Load address misaligned";
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case 5:
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return "Load access fault";
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case 6:
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return "Store/AMO address misaligned";
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case 7:
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return "Store/AMO access fault";
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case 8:
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return "Environment call from U-mode";
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case 9:
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return "Environment call from S-mode";
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case 11:
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return "Environment call from M-mode";
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case 12:
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return "Instruction page fault";
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case 13:
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return "Load page fault";
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case 15:
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return "Store/AMO page fault";
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default:
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return "unknown";
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}
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}
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static bool bad_stack_pointer(struct arch_esf *esf)
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{
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#ifdef CONFIG_PMP_STACK_GUARD
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@ -207,22 +222,6 @@ void _Fault(struct arch_esf *esf)
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}
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#endif /* CONFIG_USERSPACE */
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unsigned long mcause;
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__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
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#ifndef CONFIG_SOC_OPENISA_RV32M1
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unsigned long mtval;
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__asm__ volatile("csrr %0, mtval" : "=r" (mtval));
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#endif
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mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK;
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LOG_ERR("");
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LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
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#ifndef CONFIG_SOC_OPENISA_RV32M1
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LOG_ERR(" mtval: %lx", mtval);
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#endif
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unsigned int reason = K_ERR_CPU_EXCEPTION;
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if (bad_stack_pointer(esf)) {
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