This patch add arm core MPU support to ARM MPU driver.
Change-Id: I5a61da4615ae687bf42f1c9947e291ebfd2d2c1d
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds the arm core MPU interface, a common way to access the
pu functionalities by the arm zephyr kernel.
The interface can be divided in two parts:
- a core part that will be implemented by the arm_core_mpu driver and
used directly by the kernel
- a driver part that will be implemented by the mpu drivers and used by
the arm_core_mpu driver
Change-Id: I590bd284abc40d98b06fdf1efb5800903313aa00
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds initial MPU support to NXP K6x family.
The boot configuration prevents the following security issues:
* Prevent to read at an address that is reserved in the memory map.
* Prevent to write into the boot Flash/ROM.
* Prevent from running code located in SRAM.
This driver has been tested on FRDM-K64F.
Change-Id: I907168fff0c6028f1c665f1d3c224cbeec31be32
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Now that all ARM platforms have a device tree we can move selecting of
HAS_DTS up and remove any !HAS_DTS cases, as well as setting in all the
defconfigs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add defines and pinmux arrays to support more UARTs on STM32F4.
Change-Id: Ib06c549bdb2b3d7065554a0a6d1a3d15441b29c9
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
It is useless to include the pinmux for a peripheral if it is not
enabled in the Kconfig. This is unnecessary and it increases the size of
the binary.
Define macros that will default to void if the associated Kconfig is not
enabled.
Change-Id: I0857fcef335c75b8bb6d537fd859f93d5be4a228
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Clean-up the pinmux arrays as a preparatory work before adding more
pinmuxes.
This is achieved by the following two actions:
- Define the PAD macro to simplify the [x - 1] = y construct
- Reorder the declartions by bank / pin to make it easier to
locate a pin among a high number of other pins, while minimizing the
risk of conflict when two people add a new declaration for two
different pins
Change-Id: I1ca0cc4f48bcd8cfd35b331e9821935f5c855876
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add necessary Kconfig and minimal device tree in order to support
STM32F413xH variants as found on the Nucleo STM32F413 board.
Origin: Original
Change-Id: I60230c240d6acb610f16a02c62048d448476e9c5
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The bitfield determining the I/O direction already defines the pin
as either input or output, cannot be none or both at the same time
This issue was reported by Coverity
Coverity-CID: 151970
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Not all the boards (for instance the Nuclo F412) use USART1 or USART2.
Let each board enable these USARTs when really used.
Change-Id: Idfe79c724bd7b1ab154310b4a8234b52eef2298d
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Commit 87893ddf7ad4 ("soc: stm32f429zi: rename SOC config flag") renamed
SOC_STM32F429XX to SOC_STM32F429XI but the text of the option should be
changed as well to reflect this restriction in scope.
Change-Id: I2627b59f805e73d6c8a3534e0feec71a4269c9ab
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Commit 599149dfb831 ("soc: stm32f407xg: rename SOC config flag") renamed
SOC_STM32F407XX to SOC_STM32F407XG but the text of the option should be
changed as well to reflect this restriction in scope.
Change-Id: Id03529452f5ec7d7ffee214b152c4aa555e1208a
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Rename SOC_STM32F407XX to SOC_STM32F407XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file).
Change-Id: I0afa16e86b7c99b9e685004f96beeb888f9e7568
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename SOC_STM32F429XX to SOC_STM32F429XI to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)
Change-Id: Id188b7703d2bce0a3ded09132ff0f205efa9c143
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename SOC_STM32L476XX to SOC_STM32L476XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)
Change-Id: I834bb5b83c24c39e90c0492a2b22a7c7802de361
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The xC tag in the SoC reference indicates the flash size, use it in the
configuration to permit selection of correct flash size for dts.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This patch enables the generation of the ARM CMSDK UART base address
from the device tree.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This places a sentinel value at the lowest 4 bytes of a stack
memory region and checks it at various intervals, including when
servicing interrupts or context switching.
This is implemented on all arches except ARC, which supports stack
bounds checking directly in hardware.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Unline k_thread_spawn(), the struct k_thread can live anywhere and not
in the thread's stack region. This will be useful for memory protection
scenarios where private kernel structures for a thread are not
accessible by that thread, or we want to allow the thread to use all the
stack space we gave it.
This requires a change to the internal _new_thread() API as we need to
provide a separate pointer for the k_thread.
By default, we still create internal threads with the k_thread in stack
memory. Forthcoming patches will change this, but we first need to make
it easier to define k_thread memory of variable size depending on
whether we need to store coprocessor state or not.
Change-Id: I533bbcf317833ba67a771b356b6bbc6596bf60f5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The files for the Arduino Due needed to be updated to use the new
configuration when the SoC moved from the atmel_sam3 directory to
the atmel_sam/sam3x directory.
Jira: ZEP-2067
Signed-off-by: Justin Watson <jwatson5@gmail.com>
The FPGA on the MPS2 board implements 4 SBCon devices for I2C which are
connected to:
- a touchscreen controller
- the audio device (for configuration)
- both shield connectors
Change-Id: I55ca985e18b45d68f5e7421c4768dfc9bf2fcb3f
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Converted Stellaris UART driver over to utilize device tree generated
defines. Added a yaml description for the uart, and converted over the
ti_lm3s6965 SoC & qemu_cortex_m3 board port over to utilize it.
Change-Id: Ie20844eb63d2c68eb59ad4160f7f5b5a35e2943b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce a simple device tree for the TI lm3s6965 SoC and QEMU
Cortex-M3 board port. We get flash and memory base addresses and sizes
from the device tree as well as the ARM NVIC number of priority bits.
Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reorder config entries alphabetically to make it easier to add new ones.
Change-Id: Ib118405a150a408638232513fba7198b458ecfa7
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Now that all the nRF based board/SoCs have device trees, we can remove
the Kconfig bits that are now coming from device tree.
Change-Id: Ia1a870a50582d4109070d2833660f58fd6f8691f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree support for nRF51822 SoCs and Arduino 101-BLE,
Curie-BLE, BLE Nano, PCA10028-DK, and Quark-SE BLE boards. This
is minimal support for memory, flash, and UART.
Change-Id: I7e572bea537e384b6d66e520462f023ace0c9b35
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixup the nRF52840-QIAA to allow getting its SRAM & FLASH sizes from
device tree.
Change-Id: I67ecd7da5f0472402064f158030d9f97f49d7d20
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Nothing calls _ScpMainOscEnable, so lets remove it and associated files
that aren't used anymore.
Change-Id: Ibe900d039c531c4da56baa673d309ee961b09e52
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Cleanup soc code to enable UART_MCUX_LPSCI to support UART0.
Change-Id: I173febffcffc902f228946124e0434f122a67607
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds a shim layer around the mcux lpsci driver to adapt it to the Zephyr
serial interface.
Change-Id: I024f1605e3194f34bb57e8a121900e05b3085a82
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for STM32L475xG SoC as a preliminary for
Discovery IOT board support.
stm32l476.dtsi file is now including stm32l475.dtsi
since STM32L476 SoC is a STM32L475 SoC with LCD support
Change-Id: I7567255e4172231cbf4899474617ecae0cd68d64
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.
Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit disables native stm32f4x clock control
driver and enables stm32 LL clock control driver
for stm32f4 family
Jira: ZEP-2039
Change-Id: I98ba6c89c4a3a1f39658c5808cd47a2d1f344130
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit enables STM32Cube LL based driver for stm32f4 series.
This generic driver provides a unified API to clock driver for all
stm32 series.
LL API allows driver to be lightweight and to keep genericity across
stm32 family to ease further devlopment and maintenance.
Change-Id: Ie31ae8f433313787f9c9eda77de41925721d54dd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The CC3220SF is a replacement for the CC3200 SoC, comprising
a network coprocessor and Cortex-M4 MPU.
This leverages the CC3220 SDK driver peripheral library in ROM,
and some files built from ext/hal/ti/.
Jira: ZEP-1958
Change-Id: I892b212c178e05d84ff1d716dde593ced653ae6d
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Adds event based scheduling logic to the kernel. Updates
management of timeouts, timers, idling etc. based on
time tracked at events rather than periodic ticks. Provides
interfaces for timers to announce and get next timer expiry
based on kernel scheduling decisions involving time slicing
of threads, timeouts and idling. Uses wall time units instead
of ticks in all scheduling activities.
The implementation involves changes in the following areas
1. Management of time in wall units like ms/us instead of ticks
The existing implementation already had an option to configure
number of ticks in a second. The new implementation builds on
top of that feature and provides option to set the size of the
scheduling granurality to mili seconds or micro seconds. This
allows most of the current implementation to be reused. Due to
this re-use and co-existence with tick based kernel, the names
of variables may contain the word "tick". However, in the
tickless kernel implementation, it represents the currently
configured time unit, which would be be mili seconds or
micro seconds. The APIs that take time as a parameter are not
impacted and they continue to pass time in mili seconds.
2. Timers would not be programmed in periodic mode
generating ticks. Instead they would be programmed in one
shot mode to generate events at the time the kernel scheduler
needs to gain control for its scheduling activities like
timers, timeouts, time slicing, idling etc.
3. The scheduler provides interfaces that the timer drivers
use to announce elapsed time and get the next time the scheduler
needs a timer event. It is possible that the scheduler may not
need another timer event, in which case the system would wait
for a non-timer event to wake it up if it is idling.
4. New APIs are defined to be implemented by timer drivers. Also
they need to handler timer events differently. These changes
have been done in the HPET timer driver. In future other timers
that support tickles kernel should implement these APIs as well.
These APIs are to re-program the timer, update and announce
elapsed time.
5. Philosopher and timer_api applications have been enabled to
test tickless kernel. Separate configuration files are created
which define the necessary CONFIG flags. Run these apps using
following command
make pristine && make BOARD=qemu_x86 CONF_FILE=prj_tickless.conf qemu
Jira: ZEP-339 ZEP-1946 ZEP-948
Change-Id: I7d950c31bf1ff929a9066fad42c2f0559a2e5983
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Future tickless kernel patches would be inserting some
code before call to Swap. To enable this it will create
a mcro named as the current _Swap which would call first
the tickless kernel code and then call the real __swap()
Jira: ZEP-339
Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Found out that the SAM3 series is not a single series. There are actully
3 different series, 3U, 3A, and 3X.
Origin: Original
Jira: ZEP-2067
Change-Id: I61cdc826cc32dbdd25b5e6bafaada062c8ae8417
Signed-off-by: Justin Watson <jwatson5@gmail.com>
