cc3220sf: Add support for the TI CC3220SF SoC
The CC3220SF is a replacement for the CC3200 SoC, comprising a network coprocessor and Cortex-M4 MPU. This leverages the CC3220 SDK driver peripheral library in ROM, and some files built from ext/hal/ti/. Jira: ZEP-1958 Change-Id: I892b212c178e05d84ff1d716dde593ced653ae6d Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
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5 changed files with 71 additions and 4 deletions
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host=gerrit.zephyrproject.org
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port=29418
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project=zephyr.git
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defaultremote=origin
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43
arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf
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43
arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf
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# Kconfig.defconfig.cc3220sf - TI SimpleLink CC3220SF SoC
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#
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if SOC_CC3220SF
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config SOC
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string
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default cc3220sf
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config NUM_IRQS
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int
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# must be >= the highest interrupt number used
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# This includes the NWP interrupt
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default 179
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 80000000
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config TEXT_SECTION_OFFSET
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default 0x800 if XIP
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default 0x0 if !XIP
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if GPIO
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config GPIO_CC32XX
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def_bool y
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config GPIO_CC32XX_A0
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default n
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config GPIO_CC32XX_A1
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default y
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config GPIO_CC32XX_A2
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default y
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config GPIO_CC32XX_A3
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default n
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endif # GPIO
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endif # SOC_CC3220SF
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@ -9,4 +9,19 @@ config SOC_CC3200
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bool "CC3200"
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select HAS_CC3200SDK
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config SOC_CC3220SF
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bool "CC3220SF"
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select HAS_CC3220SDK
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endchoice
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if SOC_CC3220SF
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config CC3220SF_DEBUG
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bool "Prepend debug header, disabling flash verification"
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depends on XIP
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default y if XIP
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default n if !XIP
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endif # SOC_CC3220SF
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@ -2,9 +2,17 @@ CC3200 Board and Bootloader info taken from:
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* http://www.ti.com.cn/cn/lit/ug/swru367c/swru367c.pdf
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* http://www.ti.com/lit/ug/swru369c/swru369c.pdf
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Notes:
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CC3220 Info taken from:
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* http://www.ti.com/lit/ug/swru465/swru465.pdf
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Notes for CC3200:
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* CC3200 has no integrated flash Memory.
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* TI bootloader takes first 16Kb of the 256Kb SRAM, so app must start at
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0x20004000. CC3200 Kconfig must set SRAM size to 240Kb or less, since
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Zephyr computes TOP_OF_MEMORY (used for stack) based on SRAM_BASE_ADDRESS
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+ SRAM_SIZE.
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Notes for CC3220SF:
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* Text must start at 0x800 offset in flash. The first 0x800 bytes are
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reserved for the flash header.
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* See CONFIG_TEXT_SECTION_OFFSET.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, Texas Instruments Incorporated
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* Copyright (c) 2016-2017, Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <driverlib/rom_map.h>
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#include <driverlib/prcm.h>
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static int ti_cc3200_init(struct device *arg)
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static int ti_cc32xx_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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return 0;
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}
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SYS_INIT(ti_cc3200_init, PRE_KERNEL_1, 0);
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SYS_INIT(ti_cc32xx_init, PRE_KERNEL_1, 0);
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