arm: soc: ti_lm3s6965: remove dead code
Nothing calls _ScpMainOscEnable, so lets remove it and associated files that aren't used anymore. Change-Id: Ibe900d039c531c4da56baa673d309ee961b09e52 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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Kumar Gala
parent
94abb1f7fb
commit
62b0750499
3 changed files with 0 additions and 209 deletions
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@ -1,3 +1,2 @@
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obj-y += soc_config.o
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obj-y += soc.o
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obj-y += scp.o
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@ -1,44 +0,0 @@
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief TI LM3S6965 System Control Peripherals interface
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*
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*
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* Library for controlling target-specific devices present in the 0x400fe000
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* peripherals memory region.
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*
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* Currently, only enabling the main OSC with default value is implemented.
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*/
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#include <zephyr/types.h>
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#include <toolchain.h>
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#include <sections.h>
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#include "scp.h"
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/* System Control Peripheral (SCP) Registers */
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volatile struct __scp __scp_section __scp;
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/**
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*
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* @brief Enable main oscillator with default frequency of 6MHz
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*
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* @return N/A
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*/
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void _ScpMainOscEnable(void)
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{
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union __rcc reg;
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reg.value = __scp.clock.rcc.value;
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reg.bit.moscdis = 0;
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reg.bit.oscsrc = _SCP_OSC_SOURCE_MAIN;
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reg.bit.xtal = _SCP_CRYSTAL_6MHZ;
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__scp.clock.rcc.value = reg.value;
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}
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@ -1,164 +0,0 @@
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief TI LM3S6965 System Control Peripherals interface
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*
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* This module defines the System Control Peripheral Registers for TI LM3S6965
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* processor. The registers defined are in region 0x400fe000.
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*
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* System Control 0x400fe000
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*
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* These modules are not defined:
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*
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* Hibernation Module 0x400fc000
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* Internal Memory 0x400fd000
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* Hibernation Module 0x400fc000
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*
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* The registers and bit field names are taken from the 'Stellaris LM3S6965
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* Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document,
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* section 5.4/5.5, pp .184-200.
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*/
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#ifndef _SCP_H_
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#define _SCP_H_
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _SCP_OSC_SOURCE_MAIN 0
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#define _SCP_OSC_SOURCE_INTERNAL 1
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#define _SCP_OSC_SOURCE_INTERNAL_DIV4 2
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#define _SCP_OSC_SOURCE_INTERNAL_20KHZ 3
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#define _SCP_OSC_SOURCE_EXTERNAL_32KHZ 7 /* Valid with RCC2 only */
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#define _SCP_CRYSTAL_1MHZ_NOPLL 0
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#define _SCP_CRYSTAL_1_8432MHZ_NOPLL 1
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#define _SCP_CRYSTAL_2MHZ_NOPLL 2
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#define _SCP_CRYSTAL_2_4576MHZ_NOPLL 3
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#define _SCP_CRYSTAL_3_579545MHZ 4
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#define _SCP_CRYSTAL_3_6864MHZ 5
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#define _SCP_CRYSTAL_4MHZ 6
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#define _SCP_CRYSTAL_4_0964MHZ 7
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#define _SCP_CRYSTAL_4_9152MHZ 8
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#define _SCP_CRYSTAL_5MHZ 9
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#define _SCP_CRYSTAL_5_12MHZ 10
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#define _SCP_CRYSTAL_6MHZ 11 /* reset value */
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#define _SCP_CRYSTAL_6_144MHZ 12
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#define _SCP_CRYSTAL_7_3728MHZ 13
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#define _SCP_CRYSTAL_8MHZ 14
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#define _SCP_CRYSTAL_8_192MHZ 15
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union __rcc {
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u32_t value;
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struct {
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u32_t moscdis : 1 __packed;
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u32_t ioscdis : 1 __packed;
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u32_t rsvd__2_3 : 2 __packed;
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u32_t oscsrc : 2 __packed;
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u32_t xtal : 4 __packed;
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u32_t rsvd__10 : 1 __packed;
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u32_t bypass : 1 __packed;
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u32_t rsvd__12 : 1 __packed;
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u32_t pwrdn : 1 __packed;
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u32_t rsvd__14_16 : 3 __packed;
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u32_t pwmdiv : 3 __packed; /* 2**(n+1) */
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u32_t usepwmdiv : 1 __packed;
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u32_t rsvd__21 : 1 __packed;
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u32_t usesysdiv : 1 __packed;
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u32_t sysdiv : 4 __packed;
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u32_t acg : 1 __packed;
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u32_t rsvd__28_31 : 4 __packed;
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} bit;
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};
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union __rcc2 {
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u32_t value;
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struct {
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u8_t rsvd__0_3 : 4 __packed;
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u8_t oscsrc2 : 3 __packed;
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u16_t rsvd__7_10 : 4 __packed;
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u8_t bypass2 : 1 __packed;
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u8_t rsvd__12 : 1 __packed;
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u8_t pwrdn2 : 1 __packed;
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u16_t rsvd__14_22 : 9 __packed;
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u16_t sysdiv2 : 6 __packed;
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u8_t rsvd__29_30 : 2 __packed;
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u8_t usercc2 : 1 __packed;
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} bit;
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};
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struct __scp {
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u32_t did0; /* 0x000 RO Device ID*/
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u32_t did1; /* 0x004 RO Device ID*/
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u32_t dc0; /* 0x008 RO Device Capabilities */
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u32_t dc1; /* 0x00c RO Device Capabilities */
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u32_t dc2; /* 0x010 RO Device Capabilities */
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u32_t dc3; /* 0x014 RO Device Capabilities */
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u32_t dc4; /* 0x018 RO Device capabilities */
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u32_t rsvd__01c_02f[(0x30 - 0x1c) / 4];
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u32_t pborctl; /* 0x030 RW Brown-Out Reset ConTroL */
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u32_t ldopctl; /* 0x034 RW LDO Power ConTroL */
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u32_t rsvd__038_03f[(0x40 - 0x38) / 4];
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u32_t srcr0; /* 0x040 RW Software Reset Control Register */
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u32_t srcr1; /* 0x044 RW Software Reset Control Register */
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u32_t srcr2; /* 0x048 RW Software Reset Control Register */
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u32_t rsvd__04c_04f;
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u32_t ris; /* 0x050 RO Raw Interrupt Status */
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u32_t imc; /* 0x054 RW Interrupt Mask Control */
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u32_t misc; /* 0x058 RW1C Masked Int. Status & Clear */
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u32_t resc; /* 0x05C RW RESet Cause */
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struct {
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union __rcc rcc; /* 0x060 RW Run-mode Clock Configuration */
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u32_t pllcfg; /* 0x064 RW xtal-to-pll translation */
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u32_t rsvd__068_06f[(0x70 - 0x068) / 4];
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union __rcc2 rcc2; /* 0x070 RW Run-mode Clock Configuration */
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u32_t rsvd__074_0ff[(0x100 - 0x074) / 4];
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u32_t rcgc0; /* 0x100 RW Run-mode Clock Gating */
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u32_t rcgc1; /* 0x104 RW Run-mode Clock Gating */
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u32_t rcgc2; /* 0x108 RW Run-mode Clock Gating */
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u32_t rsvd__10c_10f;
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u32_t scgc0; /* 0x110 RW Sleep-mode Clock Gating */
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u32_t scgc1; /* 0x114 RW Sleep-mode Clock Gating */
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u32_t scgc2; /* 0x118 RW Sleep-mode Clock Gating */
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u32_t rsvd__11c_11f;
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u32_t dcgc0; /* 0x120 RW Deep sleep mode Clock Gating */
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u32_t dcgc1; /* 0x124 RW Deep sleep mode Clock Gating */
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u32_t dcgc2; /* 0x128 RW Deep sleep mode Clock Gating */
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u32_t rsvd__12c_143[(0x144 - 0x12c) / 4];
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u32_t
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dslpclkcfg; /* 0x144 RW Deep SLeeP CLocK ConFiGuration
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*/
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} clock;
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};
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extern volatile struct __scp __scp;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SCP_H_ */
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