michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: arm: Fix zero interrupt latency priority level

Browse source 
Change the zero latency interrupt priority level from 2 to 1.
This is the priority level that the kernel has reserved for the
zero latency IRQ feature by the _IRQ_PRIO_OFFSET constant.
The zero latency IRQ will now not be masked by the irq_lock function.

Update comments to reflect the priority levels reserved by the kernel.

Fixes: #8073

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
This commit is contained in:
Joakim Andersson 2018-05-22 14:18:22 +02:00 • committed by Anas Nashif
commit 45b75dd7ff
3 changed files with 16 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

15
arch/arm/core/irq_manage.c
View file

@ -77,26 +77,25 @@ int _arch_irq_is_enabled(unsigned int irq)
*
* The priority is verified if ASSERT_ON is enabled. The maximum number
* of priority levels is a little complex, as there are some hardware
* priority levels which are reserved: three for various types of exceptions,
* and possibly one additional to support zero latency interrupts.
* priority levels which are reserved.
*
* @return N/A
*/
void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
{
/* Hardware priority levels 0 and 1 reserved for Kernel use.
* So we add 2 to the requested priority level. If we support
* ZLI, 2 is also reserved so we add 3.
/* The kernel may reserve some of the highest priority levels.
* So we offset the requested priority level with the number
* of priority levels reserved by the kernel.
*/
#if CONFIG_ZERO_LATENCY_IRQS
/* If we have zero latency interrupts, that makes priority level 2
* a case with special semantics; it is not masked by irq_lock().
/* If we have zero latency interrupts, those interrupts will
* run at a priority level which is not masked by irq_lock().
* Our policy is to express priority levels with special properties
* via flags
*/
if (flags & IRQ_ZERO_LATENCY) {
prio = 2;
prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
} else {
prio += _IRQ_PRIO_OFFSET;
}

3
arch/arm/include/cortex_m/exc.h
View file

@ -27,6 +27,7 @@ extern "C" {
#else
#include <arch/arm/cortex_m/cmsis.h>
#include <arch/arm/cortex_m/exc.h>
#include <irq_offload.h>
#ifdef CONFIG_IRQ_OFFLOAD
@ -78,8 +79,6 @@ static ALWAYS_INLINE int _IsInIsr(void)
;
}
#define _EXC_SVC_PRIO 0
#define _EXC_FAULT_PRIO 0
/**
* @brief Setup system exceptions
*

17
include/arch/arm/cortex_m/exc.h
View file

@ -21,21 +21,20 @@ extern "C" {
/* for assembler, only works with constants */
#define _EXC_PRIO(pri) (((pri) << (8 - CONFIG_NUM_IRQ_PRIO_BITS)) & 0xff)
#ifdef CONFIG_ZERO_LATENCY_IRQS
#define _ZERO_LATENCY_IRQS_RESERVED_PRIO 1
#else
#define _ZERO_LATENCY_IRQS_RESERVED_PRIO 0
#endif
#if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS)
#define _EXCEPTION_RESERVED_PRIO 1
#else
#define _EXCEPTION_RESERVED_PRIO 0
#endif
#define _IRQ_PRIO_OFFSET \
(_ZERO_LATENCY_IRQS_RESERVED_PRIO + \
_EXCEPTION_RESERVED_PRIO)
#define _EXC_SVC_PRIO 0
#define _EXC_FAULT_PRIO 0
#ifdef CONFIG_ZERO_LATENCY_IRQS
#define _EXC_ZERO_LATENCY_IRQS_PRIO 1
#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + 1)
#else
#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO)
#endif
#define _EXC_IRQ_DEFAULT_PRIO _EXC_PRIO(_IRQ_PRIO_OFFSET)