Remove all xPSR-related registers from struct __cpu_context, and the
associated save/restore code in S2RAM code, as they are not needed:
* EPSR and IPSR are read-only - they cannot be "restored"
* Bits N, V, Z, C, V, Q, and GE (if DSP Extension is implemented) of APSR
could be restored, but this is not needed as the AAPCS indicates these
bits to be "undefined on entry to or return from a public interface"
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The STKALIGN mask is not present for CONFIG_ARMV8_M_BASELINE as
well as CONFIG_ARMV8_M_MAINLINE. So filter out that check when
setting the sp for ARM core dumps.
Signed-off-by: Mark Holden <mholden@meta.com>
The FPU is already disabled by the z_arm_svc function when the first
thread starts. Therefore, disabling the FPU at boot is unnecessary for
lazy FPU; instead, it must be enabled to handle floating-point instructions
before the lazy FPU works.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.
The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.
During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.
Signed-off-by: Mark Holden <mholden@meta.com>
This change was in the same commit previously reverted and seem to be
unrelated and should not be reverted.
Fixes the problem:
..... /swap_helper.S:432:(.text.z_arm_svc+0x26):
relocation truncated to fit: R_ARM_THM_JUMP11 against symbol
`z_arm_int_exit' defined in .text._HandlerModeExit section in
....core/cortex_m/libarch__arm__core__cortex_m.a(exc_exit.c.obj)
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add "memory" to the clobber list"
From GCC 14 the compiler optimizes away memory accesses that do not
impact the asm block. Adding the memory to the clobber list lets the
compiler know that the memory state is to be preserved.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Move the _main argument to the input list rather than the output one on
the asm block and change the spec to "r". The ASM block does not return,
so it does not make sense for it to expect any output.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The coprocessor number in ARM `mrc` and `mcr` instructions must be prefixed
with `p`.
GNU assembler allows specifying coprocessor number without the `p` prefix;
but, LLVM assembler is more picky about this and prints out "invalid
instruction" error otherwise.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Added casts to uint32_t in arch_timing_cycles_get() to handle the
wrap-around of the 32-bit cycle counter correctly.
Signed-off-by: Simon Tomschik <simon.tomschik@askgroup.global>
What is changed?
Updated the condition thats prevents mpu config for null dereference.
Added a new check so that mpu is configured for null dereference if
devicetree contains a memory-region node with:
- node address starting at 0
- size covered by the node is more than the null dereference page
size (0x400) and
- contains a memory-attr
Why is the change needed?
The check relied on flash base address to align with 0 for
configuring the mpu for null dereference but, a device tree
could have a flash starting at an address other than 0 and
still need the mpu config for null dereference.
The new extra check provides a way to connfigure mpu for
null dereference even if flash base address is not 0.
Note, though this change helps with mpu config for new boards having
flash address other than 0, this change does not change existing
behaviour for existing boards.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The S2RAM procedure requires marker checking after reset.
Such checking is performed on very early stage of the system initialization
and must ensure that the stack is not used due to the TLS pointer which is
not initialized yet.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
What is changed?
1. Updated the data sync barrier to make sure the other parameters of
`arm_cpu_boot_params` are updated before updating its member `mpidr`
2. Updated the MPIDR affinity level mask to account for affinity level
1 and 2 along with level 0.
Why do we need this change?
1. As reported in issue #76182, on Cortex_A_R, the current code
execution fails to consider the correct sequence of data sync
barrier and cache maintenece for the code to work on non cache
coherent cores in SMP enabled mode.
The secondary cores are waiting in a loop for primary core to set
`arm_cpu_boot_params.mpidr`. As soon as primary core set this,
the secondary cores start reading other parameters from the
`arm_cpu_boot_params` however, the existing position of DSB
instruction doesn't guarantee that `arg`, `cpu_num` and other
parameters of `arm_cpu_boot_params` would be updated before `mpidr`
is udpated and this could lead to a unpredicatble behaviour so,
we need to move the DSB instruction.
2. The affinity level mask is updated because it didn't account for
level 1 to identify individual cores within a cluster and
level 2 to identify different clusters within the system which can
lead to an incorrect conversion between mpidr to core-id.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
What is changed?
Secondary cores can now boot successfully on cache and non-cache
coherent systems if the Zephyr image/vector table is loaded at an
address other than the default address 0x0.
How is it changed?
1. By calling the relocate_vector() from reset.S as part of EL1 reset
initialization instead of prep_c to have VBAR set for all cores and
not just for the primary core.
2. Remove dead code under CONFIG_SW_VECTOR_RELAY and
CONFIG_SW_VECTOR_RELAY_CLIENT.
Why do we need this change?
1. As reported in issue #76182, on Cortex_ar, VBAR is set only for
the primary cores while VBAR for the secondary cores are left with
default value 0.
This results in Zephyr not booting on secondary cores if the vector
table for secondary cores is loaded at an address other than 0x0.
VBAR is set in relocate_vector() so we move it to reboot.c which is
better suited to have configs related to system control block.
2. The two SW_VECTOR_RELAY configs have a direct dependency on
CONFIG_CPU_CORTEX_M, which is disabled while compiling for
Cortex-A and Cortex-R hence leading to a dead code.
How is the change verified?
Verified with fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
This reverts commit ec7943bb18.
This commit introduced a regression.
Let's revert it so we do not block development in main.
For more information see:
https://github.com/zephyrproject-rtos/zephyr/issues/79594
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.
The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.
During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.
Signed-off-by: Mark Holden <mholden@meta.com>
Enable Cortex R8 support, similar to Cortex-R5.
Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Do not use SYS_INIT for initializing irq_offload when enabled, instead
using a new interface that is called during the boot process for all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a new call for initializing cache on architectures that need that.
Avoid using SYS_INIT for this and instead call the hook in a fixed place
and run if implemented.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Otherwise we can't escape from DEPRECATED being selected, and so getting
build warnings. It doesn't make sense that the option replacing the
deprecated one is used to automatically enable it.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce soc and board hooks to replace arch specific code
and replace usages of SYS_INIT for platform initialization.
include/zephyr/platform/hooks.h introduces the hooks to be implemented
by boards and SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The r0 register holds the system_off function pointer. As r0 is a scratch
register, the pointer needs to moved to a preserved register before
branching to a (custom) marker function.
Furthermore, in accordance to rule 6.2.1.2 of aapcs32, the stack pointer
needs to align on 8 bytes. Hence r0 is pushed to the stack in addition to
the lr register, before calling the public interface of checking the
s2ram marker.
Signed-off-by: Hessel van der Molen <hvandermolen@dexels.com>
This commit fixes potential unpredictable behavior, caused by using
the ^ form of ldmia instruction, while exiting an exception in SMP
mode on Cortex-A/R.
Change:
Use "pop" instead of "ldmia" to restore user mode registers while
exiting from an exception via `z_arm_cortex_ar_exit_exc`.
Reason for change:
Processor mode is always set to system (MODE_SYS) before calling
`z_arm_cortex_ar_exit_exc` and hence, the user mode register can be
accessed directly without the ^ form of the instruction. Also, LDMIA
instruction is UNPREDICTABLE in SYStem mode.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
This commit fixes the unpredictable behavior, caused by using the
^ form of stmdb instruction, while entering an exception in SMP mode
on Cortex-A/R.
Change:
Use "push" instead of "stmdb" to store user mode registers on
stack while entering an exception in SYStem mode.
Reason for change:
As reported in discussion/#75339, processor is already in SYS mode
after entering `z_arm_cortex_ar_enter_exc()` in an exception and
using stmdb is UNPREDICTABLE in system mode. Also, the user mode
register can be accessed directly without the ^ form of the
instruction. The solution suggested to fix this is to use
`stmdb sp!, {r0-r3, r12, lr}` which can save the user registers,
update the SP and avoid an extra instruction.
We use "push {}" instruction instead since it is the preferred
mnemonic over `stmdb`.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Port of similar change in arm64 that eliminates exclusive load/store
instructions, which may not work when MMU/MPU/cache are disabled.
Based on: 7904c6f0f3
Signed-off-by: Stan Skowronek <stan@corellium.com>
custom arch_cpu_idle and arch_cpu_atomic_idle implementation was done
differently on different architectures. riscv implemented those as weak
symbols, xtensa used a kconfig and all other architectures did not
really care, but this was a global kconfig that should apply to all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clear the UNALIGN_TRP bit in the CCR register, if the config
CONFIG_TRAP_UNALIGNED_ACCESS is not set.
Despite the fact that the reset value of UNALIGN_TRP is 0, always clear
the bit. It is useful in double image systems. The new image can't rely
on settings left by the previous image.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Calls to other function may clobber ip & lr too so these register need to
be added to the clobberlist.
r3 is not actually used in z_arm_switch_to_main_no_multithreading so it is
also removed from the clobber list.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Sets the property `PROPERTY_OUTPUT_FORMAT` to `elf32-bigarm` when
`CONFIG_BIG_ENDIAN` is set to `y`.
Signed-off-by: Sigmund Klåpbakken <sigmundklaa@outlook.com>
When this bit is not set, it defaults to 0 (little endian). This
causes issues for big-endian devices, as data will be accessed using
little endian.
Signed-off-by: Sigmund Klåpbakken <sigmundklaa@outlook.com>
Add initial support for the Cortex-M85 Core which is an implementation
of the Armv8.1-M mainline architecture.
The support is based on the Cortex-M55 support that already exists in
Zephyr.
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
isr_wrapper has been converted to C but this inline comment was not
updated. This fixes the out-of-sync comment.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Move this to a call in the init process. arch_* calls are no services
and should be called consistently during initialization.
Place it between PRE_KERNEL_1 and PRE_KERNEL_2 as some drivers
initialized in PRE_KERNEL_2 might depend on SMP being setup.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a prompt to ROMSTART_RELOCATION_ROM configs to allow
projects config file selection.
This simplifies the usage in samples/app for board porting.
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
Memory region defined in devicetree can have attributes
that are not intended to be parsed by MPU library,
but might be valid for other components.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.
As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.
Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases. These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Make `struct arch_esf` compulsory for all architectures by
declaring it in the `arch_interface.h` header.
After this commit, the named struct `z_arch_esf_t` is only used
internally to generate offsets, and is slated to be removed
from the `arch_interface.h` header in the future.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
