Commit graph

2358 commits

Author SHA1 Message Date
Samuel Chee
d9eed167d0 arm: mpu: Unify ARM_MPU kconfig definitions
Previously, there were two separate Kconfig definitions
of ARM_MPU located at:
- arch/arm/core/mpu/Kconfig
- arch/arm64/core/cortex_r/Kconfig

This lead to incomplete default settings and unexpected
missing configurations.

This commit combines the two into a single unified definition
now located at arch/common/Kconfig to prevent this.

Signed-off-by: Samuel Chee <samche01@arm.com>
2025-01-09 11:55:22 +01:00
Hessel van der Molen
8316f097ce arch: arm: cortex_m: pm_s2ram: fix system_off rv as rv of s2ram_suspend
The return value of the system_off call is overwritten by the the call to
pm_s2ram_mark_check_and_clear. As arch_pm_s2ram_suspend needs to specify
why system_off failed, we need to make sure the rv of system_off is moved
to a safe register before calling pm_s2ram_mark_check_and_clear and moved
to r0 als rv of arch_pm_s2ram_suspend when the suspend call exits.

Signed-off-by: Hessel van der Molen <hvandermolen@dexels.com>
2025-01-03 17:11:09 +00:00
Stephanos Ioannidis
734fa185c8 arch: arm: cortex_m: Use Thumb-1 compatible 'mov reg, imm' mnemonic
The ARM Thumb-1 instruction set, used by ARMv6-M and ARMv8-M Baseline
cores, does not have a valid encoding for "immediate-to-register move
without affecting flags" instruction (i.e. `mov reg, imm`), and the only
valid variant of immediate-to-register move instruction for it is `movs`,
which affects the flags.

Since none of the register initialisation instructions used here are
flag-sensitive in their context, this commit changes `mov` to `movs`.

This fixes the compilation errors with Clang/LLVM, which is more picky
about the `mov` mnemonic usage and prints out an "invalid instruction"
error when `mov reg, imm` is specified in Thumb-1 mode.

Note that GNU assembler implicitly converts `mov reg, imm` to `movs reg,
imm` when assembling in Thumb-1 mode.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2024-12-13 11:35:06 +01:00
Peter Mitsis
909ff45f0c kernel: arch: move arch_swap() declaration
Moves the arch_swap() declaration out of kernel_arch_interface.h
and into the various architectures' kernel_arch_func.h. This
permits the arch_swap() to be inlined on ARM, but extern'd on
the other architectures that still implement arch_swap().

Inlining this function on ARM has shown at least a +5% performance
boost according to the thread_metric benchmark on the disco_l475_iot1
board.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2024-12-11 21:33:49 +01:00
Grant Ramsay
31b54e7cee arch: arm: cortex_m: Include TBLBASE in VTOR mask if present
In some Cortex-M3 implementations SCB_VTOR bit[29] is called
the TBLBASE bit.
This enables setting VTOR to an SRAM address for qemu_cortex_m3

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2024-12-10 03:16:23 +00:00
Manuel Argüelles
87798f9e16 arch: arm: rename CPU_HAS_NXP_MPU to align with binding
Following the binding rename to "nxp,sysmpu", update the Kconfig
option to align with the binding name and to better reflect the
option's purpose.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-12-06 22:23:06 +01:00
Alexandru Lastur
9cebb3ff63 arm: mpu: Remove FLASH_0 mpu region when XIP=n
When not using CONFIG_XIP (CONFIG_XIP=n)
the FLASH_0 mpu region needs to be removed,
otherwise it will have the default base
address = 0, which means that MPU will try
to configure the region with address 0.
We don't want this as in some situations
address 0 can be a restricted memory region
such as ROM code.

Signed-off-by: Alexandru Lastur <alexandru.lastur@nxp.com>
2024-12-06 18:20:48 +01:00
Dat Nguyen Duy
2b2b41d775 arch: arm: cortex_a_r: add Kconfig options for cache segregation
On Arm Cortex R52, cache segregation policy controls the
number of L1 I/D cache ways that are allocated to Flash
and AXIM interface. Adding Kconfig options for configuring
it.

Writing to IMP_CSCTRL is only permitted before the caches
have been enabled, following a system reset.

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2024-11-26 15:43:45 -05:00
Yong Cong Sin
b1def7145f arch: deprecate _current
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-11-23 20:12:24 -05:00
Sudan Landge
c99243c8ce arch: arm: cleanup of soc flags in arch
What is changed?

Use CMSIS SystemCoreClock via a dedicated flag instead of using
soc flags.

Why do we need this change?

This change is part of cleaning soc specific code out of arch folder.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2024-11-16 15:56:11 -05:00
Yong Cong Sin
de347a4e07 init: support per-core init hook
Allow SoC to implement their custom per-core initialization function by
selecting `CONFIG_SOC_PER_CORE_INIT_HOOK` and implement
`soc_per_core_init_hook()`.

Signed-off-by: Maxim Adelman <imax@meta.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-11-16 14:04:25 -05:00
Mathieu Choplain
f27323a45d arch: arm: cortex_m: pm_s2ram: add support for all architectures
Extend the ARM M-profile suspend-to-RAM implementation to be compatible
with all versions of the M-profile supported by Zephyr: ARMv6-M, ARMv7-M,
and ARMv8-M Baseline.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2024-11-16 14:00:44 -05:00
Mathieu Choplain
18f41aa63c arch: arm: cortex_m: pm_s2ram: wrap context save/restore in macros
Wrap the CPU register save/restore operations (GPR and special registers)
in macros to make core logic simpler to follow. This is also a preparatory
step to introduce ARMv6-M and ARMv7-M support.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2024-11-16 14:00:44 -05:00
Mathieu Choplain
041714cb37 arch: arm: cortex_m: pm_s2ram: use macros to access struct __cpu_context
Use macros to wrap the interaction between the assembly code and the
struct __cpu_context. This helps making the assembly more readable.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2024-11-16 14:00:44 -05:00
Mathieu Choplain
7dd7dffe33 arch: arm: cortex_m: pm_s2ram: ignore xPSR
Remove all xPSR-related registers from struct __cpu_context, and the
associated save/restore code in S2RAM code, as they are not needed:

* EPSR and IPSR are read-only - they cannot be "restored"
* Bits N, V, Z, C, V, Q, and GE (if DSP Extension is implemented) of APSR
  could be restored, but this is not needed as the AAPCS indicates these
  bits to be "undefined on entry to or return from a public interface"

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2024-11-16 14:00:44 -05:00
Mark Holden
94c1079560 arch: arm: Don't use STKALIGN mask on ARMv8-M Baseline
The STKALIGN mask is not present for CONFIG_ARMV8_M_BASELINE as
well as CONFIG_ARMV8_M_MAINLINE. So filter out that check when
setting the sp for ARM core dumps.

Signed-off-by: Mark Holden <mholden@meta.com>
2024-11-14 17:27:17 -06:00
Ha Duong Quang
6984237c06 arch: arm: core: cortex_a_r: enable the VFP unit on boot for FPU_SHARING
The FPU is already disabled by the z_arm_svc function when the first
thread starts. Therefore, disabling the FPU at boot is unnecessary for
lazy FPU; instead, it must be enabled to handle floating-point instructions
before the lazy FPU works.

Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
2024-11-06 10:18:59 -08:00
Mark Holden
8bd4f244b0 coredump: ARM: Ensure sp in dump is set as gdb expects
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.

The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.

During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.

Signed-off-by: Mark Holden <mholden@meta.com>
2024-11-06 10:17:59 -08:00
Anas Nashif
d9bc0b60b9 arm: cortex_m: restore fix for loading z_arm_int_exit
This change was in the same commit previously reverted and seem to be
unrelated and should not be reverted.

Fixes the problem:

..... /swap_helper.S:432:(.text.z_arm_svc+0x26):
relocation truncated to fit: R_ARM_THM_JUMP11 against symbol
`z_arm_int_exit' defined in .text._HandlerModeExit section in
....core/cortex_m/libarch__arm__core__cortex_m.a(exc_exit.c.obj)

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-11-01 16:13:58 -07:00
Anas Nashif
e646b7f3bb Revert "arch: arm: cortex_m: move part of swap_helper to C"
This reverts commit 773739a52a.

Fixes #80701

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-11-01 13:54:44 -05:00
Anas Nashif
7aa4032ac6 Revert "arch: arm: cortex_m: restore comment lost in translation"
This reverts commit 7d7616214b.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-11-01 13:54:44 -05:00
Fabio Baltieri
63890e2526 arch: arm: cortex_m: add memory to the clobber list
Add "memory" to the clobber list"

From GCC 14 the compiler optimizes away memory accesses that do not
impact the asm block. Adding the memory to the clobber list lets the
compiler know that the memory state is to be preserved.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2024-10-31 14:16:48 -05:00
Fabio Baltieri
7015a0ee37 arch: arm: cortex_m: move _main in input list
Move the _main argument to the input list rather than the output one on
the asm block and change the spec to "r". The ASM block does not return,
so it does not make sense for it to expect any output.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2024-10-31 14:16:48 -05:00
Stephanos Ioannidis
cd9ddc95a8 arch: arm: cortex_a_r: Fix mrc/mcr instruction usage
The coprocessor number in ARM `mrc` and `mcr` instructions must be prefixed
with `p`.

GNU assembler allows specifying coprocessor number without the `p` prefix;
but, LLVM assembler is more picky about this and prints out "invalid
instruction" error otherwise.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2024-10-29 16:02:16 -07:00
Simon Tomschik
1647ad5c0a timing: fix ARM Cortex-M timing functions wrap-around issue
Added casts to uint32_t in arch_timing_cycles_get() to handle the
wrap-around of the 32-bit cycle counter correctly.

Signed-off-by: Simon Tomschik <simon.tomschik@askgroup.global>
2024-10-29 07:09:34 -05:00
Sudan Landge
f2e115cca3 arch: arm: fix null pointer dereference check test
What is changed?
Updated the condition thats prevents mpu config for null dereference.
Added a new check so that mpu is configured for null dereference if
devicetree contains a memory-region node with:
 - node address starting at 0
 - size covered by the node is more than the null dereference page
   size (0x400) and
 - contains a memory-attr

Why is the change needed?
The check relied on flash base address to align with 0 for
configuring the mpu for null dereference but, a device tree
could have a flash starting at an address other than 0 and
still need the mpu config for null dereference.
The new extra check provides a way to connfigure mpu for
null dereference even if flash base address is not 0.

Note, though this change helps with mpu config for new boards having
flash address other than 0, this change does not change existing
behaviour for existing boards.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2024-10-26 03:58:05 +01:00
Adam Kondraciuk
474d4c3249 arch: arm: cortex_m: pm_s2ram: Rework S2RAM mark functions
The S2RAM procedure requires marker checking after reset.
Such checking is performed on very early stage of the system initialization
and must ensure that the stack is not used due to the TLS pointer which is
not initialized yet.

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
2024-10-25 13:58:37 +02:00
Sudan Landge
8bdd45be47 arch: arm: cortex_a_r: smp: minor fix for non cache coherent cores
What is changed?
1. Updated the data sync barrier to make sure the other parameters of
   `arm_cpu_boot_params` are updated before updating its member `mpidr`
2. Updated the MPIDR affinity level mask to account for affinity level
   1 and 2 along with level 0.

Why do we need this change?
1. As reported in issue #76182, on Cortex_A_R, the current code
   execution fails to consider the correct sequence of data sync
   barrier and cache maintenece for the code to work on non cache
   coherent cores in SMP enabled mode.
   The secondary cores are waiting in a loop for primary core to set
   `arm_cpu_boot_params.mpidr`. As soon as primary core set this,
    the secondary cores start reading other parameters from the
   `arm_cpu_boot_params` however, the existing position of DSB
   instruction doesn't guarantee that `arg`, `cpu_num` and other
   parameters of `arm_cpu_boot_params` would be updated before `mpidr`
   is udpated and this could lead to a unpredicatble behaviour so,
   we need to move the DSB instruction.
2. The affinity level mask is updated because it didn't account for
   level 1 to identify individual cores within a cluster and
   level 2 to identify different clusters within the system which can
   lead to an incorrect conversion between mpidr to core-id.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2024-10-11 13:17:25 -04:00
Sudan Landge
ac2de3fa7c arch: arm: cortex_a_r: Set VBAR for all cores
What is changed?
Secondary cores can now boot successfully on cache and non-cache
coherent systems if the Zephyr image/vector table is loaded at an
address other than the default address 0x0.

How is it changed?
1. By calling the relocate_vector() from reset.S as part of EL1 reset
   initialization instead of prep_c to have VBAR set for all cores and
   not just for the primary core.
2. Remove dead code under CONFIG_SW_VECTOR_RELAY and
   CONFIG_SW_VECTOR_RELAY_CLIENT.

Why do we need this change?
1. As reported in issue #76182, on Cortex_ar, VBAR is set only for
   the primary cores while VBAR for the secondary cores are left with
   default value 0.
   This results in Zephyr not booting on secondary cores if the vector
   table for secondary cores is loaded at an address other than 0x0.
   VBAR is set in relocate_vector() so we move it to reboot.c which is
   better suited to have configs related to system control block.
2. The two SW_VECTOR_RELAY configs have a direct dependency on
   CONFIG_CPU_CORTEX_M, which is disabled while compiling for
   Cortex-A and Cortex-R hence leading to a dead code.

How is the change verified?
Verified with fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2024-10-11 13:17:25 -04:00
Alberto Escolar Piedras
b29f9f21bc Revert "coredump: ARM: Ensure sp in dump is set as gdb expects"
This reverts commit ec7943bb18.
This commit introduced a regression.
Let's revert it so we do not block development in main.
For more information see:
https://github.com/zephyrproject-rtos/zephyr/issues/79594

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2024-10-09 13:42:19 +02:00
Mark Holden
ec7943bb18 coredump: ARM: Ensure sp in dump is set as gdb expects
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.

The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.

During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.

Signed-off-by: Mark Holden <mholden@meta.com>
2024-10-09 09:41:00 +02:00
Yong Cong Sin
52a202309b zephyr: bulk update to DT_NODE_HAS_STATUS_OKAY
Change instances of:

DT_NODE_HAS_STATUS(<node_id>, okay)

to

DT_NODE_HAS_STATUS_OKAY(<node_id>)

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-10-03 17:06:52 +01:00
Krzysztof Sychla
5d76b563ea arch: Add Cortex-R8 support
Enable Cortex R8 support, similar to Cortex-R5.

Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
2024-10-01 09:58:22 +02:00
Anas Nashif
7e225efab7 arch: initialize irq_offload during boot, do not use SYS_INIT
Do not use SYS_INIT for initializing irq_offload when enabled, instead
using a new interface that is called during the boot process for all
architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Anas Nashif
c9f7b512da arm: init null pointer detection in prep_c, do not use SYS_INIT
Do not use SYS_INIT for initializing null pointer detection, call
directly in prep_c.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Anas Nashif
6ec74d02b6 cache: add new interface arch_cache_init() for initializing cache
Add a new call for initializing cache on architectures that need that.
Avoid using SYS_INIT for this and instead call the hook in a fixed place
and run if implemented.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Gerard Marull-Paretas
a056b608f2 arch: arm: do not enable PLATFORM_SPECIFIC_INIT if SOC_RESET_HOOK=y
Otherwise we can't escape from DEPRECATED being selected, and so getting
build warnings. It doesn't make sense that the option replacing the
deprecated one is used to automatically enable it.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-09-16 15:12:18 -04:00
Adam Wojasinski
44782ad2c1 llext: Move arm-specific relocation names from generic LLEXT file
Moved symbol definitions to the pleace where they are used.

Signed-off-by: Adam Wojasinski <awojasinski@baylibre.com>
2024-09-12 14:48:55 +02:00
Pisit Sawangvonganan
56b6ccb2f4 style: arch: comply with MISRA C:2012 Rule 15.6
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
2024-09-11 07:40:35 -04:00
Anas Nashif
81cf87001c arch: arm: select PLATFORM_RESET_HOOK if is PLATFORM_SPECIFIC_INIT set
Temporary until usage of PLATFORM_SPECIFIC_INIT is removed in modules.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-09 10:07:33 +02:00
Anas Nashif
f519dd1411 arch: arm: replace PLATFORM_SPECIFIC_INIT with PLATFORM_RESET_HOOK
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.

Replace z_arm_platform_init() with platform_reset().

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-09 10:07:33 +02:00
Anas Nashif
e260d03686 init: introduce soc and board hooks
Introduce soc and board hooks to replace arch specific code
and replace usages of SYS_INIT for platform initialization.

include/zephyr/platform/hooks.h introduces the hooks to be implemented
by boards and SoCs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-09 10:07:33 +02:00
Hessel van der Molen
2590c48d40 arch: arm: cortex_m: pm_s2ram: save system_off before s2ram marking
The r0 register holds the system_off function pointer. As r0 is a scratch
register, the pointer needs to moved to a preserved register before
branching to a (custom) marker function.

Furthermore, in accordance to rule 6.2.1.2 of aapcs32, the stack pointer
needs to align on 8 bytes. Hence r0 is pushed to the stack in addition to
the lr register, before calling the public interface of checking the
s2ram marker.

Signed-off-by: Hessel van der Molen <hvandermolen@dexels.com>
2024-08-22 14:21:07 -04:00
Sudan Landge
b3fe647eaf arch: arm: cortex_a_r: Fix restore of registers while exiting exception
This commit fixes potential unpredictable behavior, caused by using
the ^ form of ldmia instruction, while exiting an exception in SMP
mode on Cortex-A/R.

Change:
Use "pop" instead of "ldmia" to restore user mode registers while
exiting from an exception via `z_arm_cortex_ar_exit_exc`.

Reason for change:
Processor mode is always set to system (MODE_SYS) before calling
`z_arm_cortex_ar_exit_exc` and hence, the user mode register can be
accessed directly without the ^ form of the instruction. Also, LDMIA
instruction is UNPREDICTABLE in SYStem mode.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2024-08-15 12:10:42 -04:00
Sudan Landge
6d8deac010 arch: arm: cortex_a_r: Fix usage of stmdb while entering an exception
This commit fixes the unpredictable behavior, caused by using the
^ form of stmdb instruction, while entering an exception in SMP mode
on Cortex-A/R.

Change:
Use "push" instead of "stmdb" to store user mode registers on
stack while entering an exception in SYStem mode.

Reason for change:
As reported in discussion/#75339, processor is already in SYS mode
after entering `z_arm_cortex_ar_enter_exc()` in an exception and
using stmdb is UNPREDICTABLE in system mode. Also, the user mode
register can be accessed directly without the ^ form of the
instruction. The solution suggested to fix this is to use
`stmdb sp!, {r0-r3, r12, lr}` which can save the user registers,
update the SP and avoid an extra instruction.
We use "push {}" instruction instead since it is the preferred
mnemonic over `stmdb`.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2024-08-15 12:10:42 -04:00
Stan Skowronek
f74592dcde arch: arm: Use voting lock for multi-core boot race condition
Port of similar change in arm64 that eliminates exclusive load/store
instructions, which may not work when MMU/MPU/cache are disabled.

Based on: 7904c6f0f3

Signed-off-by: Stan Skowronek <stan@corellium.com>
2024-08-15 11:58:01 -04:00
Anas Nashif
a91c6e56c8 arch: use same syntax for custom arch calls
Use same Kconfig syntax for those  custom arch call.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-08-12 12:43:36 +02:00
Anas Nashif
7f52fc4188 arch: custom cpu_idle and cpu_atomic harmonization
custom arch_cpu_idle and arch_cpu_atomic_idle implementation was done
differently on different architectures. riscv implemented those as weak
symbols, xtensa used a kconfig and all other architectures did not
really care, but this was a global kconfig that should apply to all
architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-08-12 12:43:36 +02:00
Dawid Niedzwiecki
f39d8bbe2c arm: clear UNALIGN_TRP bit in CCR register
Clear the UNALIGN_TRP bit in the CCR register, if the config
CONFIG_TRAP_UNALIGNED_ACCESS is not set.

Despite the fact that the reset value of UNALIGN_TRP is 0, always clear
the bit. It is useful in double image systems. The new image can't rely
on settings left by the previous image.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2024-08-12 12:43:16 +02:00
Pieter De Gendt
ad63ca284e kconfig: replace known integer constants with variables
Make the intent of the value clear and avoid invalid ranges with typos.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2024-07-27 20:49:15 +03:00