Commit graph

2358 commits

Author SHA1 Message Date
Patryk Duda
cf55f8329e core: aarch32: Fix standard for _Float16 in CONFIG_FP16 help message
Both Clang[1] and GCC[2] says that _Float16 type is defined by
ISO/IEC TS 18661-3:2015 not the IEEE 754-2008. Fix help message under
FP16 config option.

[1] https://clang.llvm.org/docs/LanguageExtensions.html#half-precision-floating-point
[2] https://gcc.gnu.org/onlinedocs/gcc/Half-Precision.html

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2023-08-01 11:24:07 +02:00
Wilfried Chauveau
965d30537f arch: arm: cortex_m: fault: Improve handling of fault escalation on armv6-m
The current implementation causes a lockup of the core when the exception
originates from an invalid/unreachable pc. This fix first verifies on
armv6-m and armv8-m.base that pc was in an expected runnable region,
namely:

- .text
- .ramfunc
- .itcm

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-07-13 09:22:46 +02:00
Andrzej Kuros
abd90085ac soc: arm: nrf53: workaround pop lr after wfi crash
On nRF5340 net core it was observed that when `wfi` instruction was
followed by `pop {r0, lr}` in the `arch_cpu_idle` function,
the value of `lr` sometimes got read as 0 from memory despite
having correct value stored in the memory.

This commit inserts additional `nop` instruction after waking up
to delay access to the memory.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-07-07 14:32:27 +02:00
Gerard Marull-Paretas
0d4e5bf67f arch: arm: nmi: simplify NMI initialization
Zephyr provides a default NMI handler (`z_SysNmiOnReset`), which will
basically call `wfi` endlessly. It is allowed to override such handler
when CONFIG_RUNTIME_NMI=y, via `z_arm_nmi_set_handler`. However,
enabling such option also provided `z_arm_nmi_init` (via `NMI_INIT()`),
which basically sets the handler to `DefaultHandler` (a new handler that
basically printks and reboots). This is strictly not needed, and
independent of the runtime NMI option. As a result, most SoCs were
blindly calling `NMI_INIT()`, probably because of a copy&paste effect.
In the majority of cases, this was a no-op, but most SoCs do IRQ
enable/disable, making this even more convoluted. To make things worse,
the init call is expected to run after console has been initialized (for
printk to work?), but most SoCs just called it in PRE_KERNEL_1+0.

This patch just drops this NMI initializer API, and leaves only the
handler set call when CONFIG_RUNTIME_NMI=y.

NMI_INIT() dummy definition is left in this patch to preserve
bisectability, will be dropped later.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-07-05 09:15:36 +02:00
Gerard Marull-Paretas
33b116407b arch: arm: cortex_m: scb: fix MPU code compilation guards
The implementation of `z_arm_clear_arm_mpu_config` was compiled for all
ARM cores that declare to have an MPU. However, we only want to compile
it if the MPU is actually enabled.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-06-29 23:46:39 +02:00
Huifeng Zhang
c1ecb8faaa arch: arm: enable FPU and FPU sharing for v8r aarch32
This commit is to enable FPU and FPU_SHARING for v8r aarch32.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
Huifeng Zhang
89ea503b29 arch: arm: Add support for 32 double-precision registers
This adds support for 32 double-precision registers in the context
switching of aarch32 architecture.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
Huifeng Zhang
b0612e14e0 arch: arm: save 'fpscr' in the svc and isr handler
`fpscr` is assigned from `struct __fpu_sf.fpscr` in `vfp_restore`, but it
wasn't saved into `struct __fpu_sf.fpscr` in the svc and isr handler, So
it may be a dirty value.

    - Fix it by saving `fpscr` in the svc hand isr handler.
    - Jump out if FPU isn't enabled

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
Björn Stenberg
234fec579a scripts: gen_relocate_app.py: Give sections unique names
The code_relocation feature creates generic section names that sometimes
conflict with already existing names.

This patch adds a '_reloc_' word to the created names to reduce the risk
of conflict.

This solves #54785.

Signed-off-by: Björn Stenberg <bjorn@haxx.se>
2023-06-20 16:33:49 +02:00
Carlo Caione
6f3a13d974 barriers: Move __ISB() to the new API
Remove the arch-specific ARM-centric __ISB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-24 13:13:57 -04:00
Carlo Caione
cb11b2e84b barriers: Move __DSB() to the new API
Remove the arch-specific ARM-centric __DSB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-24 13:13:57 -04:00
Carlo Caione
2fa807bcd1 barriers: Move __DMB() to the new API
Remove the arch-specific ARM-centric __DMB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-24 13:13:57 -04:00
Stephanos Ioannidis
a1d71bf05e arch: arm: aarch32: Remove CPU type dependency from CONFIG_FP16
The commit 434ca63e2f introduced the
Cortex-A and Cortex-R CPU type dependency to `CONFIG_FP16` based on
the reasoning that the hardware half-precision support is only
available on them.

While it is true that the _hardware_ half-precision support is limited
to these targets, the compiler will provide the _software_ emulation
for the targets that lack the hardware half-precision support, as
mentioned in 41fd6e003c (the original
commit that introduced `CONFIG_FP16`).

Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
2023-05-22 10:17:02 +02:00
Peter Mitsis
a6781b7f17 arch: arm: Remove unused absolute symbols
Removes ARM specific unused absolute symbols that are defined
via the GEN_ABSOLUTE_SYM() macro.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2023-04-18 10:51:28 -04:00
Ryan McClelland
2808711e35 arch: arm: aarch32: include m55 for fp16 support
The M55 supports half-precision floating point.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2023-04-17 10:20:17 +02:00
Gerard Marull-Paretas
a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Thomas Stranger
77d2490164 arch: arm: core: aarch32: rename z_NmiHandlerSet
rename the function that sets the handler for the nmi.
It should be namespaced and not camel-case:
z_NmiHandlerSet to z_arm_nmi_set_handler

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2023-04-12 08:59:36 +02:00
Kumar Gala
14d59b3b56 cortex_m: tz_ns.h: Fix compiling with arm-clang
We get the following error when building with arm-clang:

error: non-ASM statement in naked function is not supported
        __TZ_WRAP_FUNC(preface, foo1, postface);
        ^
tests/arch/arm/arm_tz_wrap_func/src/main.c:69:25: note: attribute is here
uint32_t __attribute__((naked)) wrap_foo1(uint32_t arg1, uint32_t arg2,
                        ^
1 error generated.

Remove the do/while wrapper to make this a true naked function.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2023-03-31 08:43:18 -05:00
Manuel Argüelles
98d4faf099 arch: arm: cortex_a_r: implement cache API
Implement cache management APIs for Cortex-A/R AArch32 L1 caches.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-03-29 09:03:37 +02:00
Manuel Argüelles
c08fab16cd arch: arm: move cache management sources to cortex_m directory
Current implementation of cache management APIs for ARM only applies to
Cortex-M, so move it to its own directory.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-03-29 09:03:37 +02:00
Ayan Kumar Halder
958dcf98e8 arch: arm: aarch32: Add ability to generate zImage header
The image header is compatible for zImage(32) protocol.

Offset  Value          Description
0x24    0x016F2818     Magic number to identify ARM Linux zImage
0x28    start address  The address the zImage starts at
0x2C    end address    The address the zImage ends at

As Zephyr can be built with a fixed load address, Xen/Uboot can read
the image header and decide where to copy the Zephyr image.

Also, it is to be noted that for AArch32 A/R, the vector table should
be aligned to 0x20 address. Refer ARM DDI 0487I.a ID081822, G8-9815,
G8.2.168, VBAR, Vector Base Address Register :-
Bits[4:0] = RES0.
For AArch32 M (Refer DDI0553B.v ID16122022, D1.2.269, VTOR, Vector Table
Offset Register), Bits [6:0] = RES0.
As zImage header occupies 0x30 bytes, thus it is necessary to align
the vector table base address to 0x80 (which satisfies both VBAR and
VTOR requirements).

Also, it is to be noted that not all the AArch32 M class have VTOR, thus
ARM_ZIMAGE_HEADER header depends on
CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR.
The reason being the processors which does not have VBAR or VTOR, needs
to have exception vector table at a fixed address in the beginning of
ROM (Refer the comment in arch/arm/core/aarch32/cortex_m/CMakeLists.txt)
. They cannot support any headers.

Also, the first instruction in zImage header is to branch to the kernel
start address. This is to support booting in situations where the zImage
header need not be parsed.

In case of Arm v8M, the first two entries in the reset vector should be
"Initial value for the main stack pointer on reset" and "Start address
for the reset handler" (Refer Armv8M DDI0553B.vID16122022, B3.30,
Vector tables).
In case of Armv7M (ARM DDI 0403E. ID021621, B1.5.3 The vector table),
the first entry is "SP_main. This is the reset value of the Main stack
pointer.".
Thus when v7M or v8M starts from reset, it expects to see these values
at the default reset vector location.
See the following text from Armv7M (ARM DDI 0403E. ID021621, B1-526)
"On powerup or reset, the processor uses the entry at offset 0 as the
initial value for SP_main..."

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
2023-02-27 17:34:12 +01:00
George Ruinelli
b2512d2f53 arm: Add missing include
Add missing include to prevent `'EINVAL' undeclared` when
using `CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT=y`

Signed-off-by: George Ruinelli <caco3@ruinelli.ch>
2023-02-25 07:59:56 -05:00
Peter Mitsis
9d83993db0 arch: arm: Remove unused generated offset symbols
Removes unused generated offset symbols under the ARM architecture.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2023-02-23 16:44:07 +01:00
Kumar Gala
434ca63e2f arch: arm: limit FP16 support to Cortex-A or Cortex-R
FP16 isn't something that is supported on Cortex-M so limit the
Kconfig feature to Cortex-A or Cortex-R.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2023-02-23 08:48:01 +01:00
Andrzej Głąbek
22b17e490b arch: arm: aarch32: Introduce z_arm_on_enter_cpu_idle() hook
Introduce an optional hook to be called when the CPU is made idle.
If needed, this hook can be used to prevent the CPU from actually
entering sleep by skipping the WFE/WFI instruction.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-02-21 15:03:30 +01:00
Jordan Yates
a3774fd51a arch: option to generate simplified error codes
Add an option to generate simplified error codes instead of more
specific architecture specific error codes. Enable this by default in
tests to make exception tests more generic across hardware.

Fixes #54053.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-01-27 18:09:32 +09:00
Dat Nguyen Duy
50e77c2f9a arch: arm: aarch32: cortex_a_r: disable interrupts before context switching
Ultil now Cortex A/R aarch32 implementation for context
switching expects that interrupts was disabled. This is
true if a context switching happens at thread context.

But if a context switching happens at last action during
interrupt context, this assumption is not true because the
interrupts are still enabled (to allow nesting interrupts).

Disable interrupts at the last interrupt action to ensure
the interrupts are always disabled before context switching
is processed

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2023-01-18 16:22:29 +01:00
Stephanos Ioannidis
4a64bfe351 treewide: Use CONFIG_CPP instead of CONFIG_CPLUSPLUS
This commit updates all in-tree code to use `CONFIG_CPP` instead of
`CONFIG_CPLUSPLUS`, which is now deprecated.

Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
2023-01-13 17:42:55 -05:00
Jordan Yates
35e78c4502 arch: arm: return arm specific fatal error reasons
Return specific fault reasons instead of the generic
`K_ERR_CPU_EXCEPTION`, which provides minimal debugging aid.

Fixes #53093.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-01-12 10:01:05 +01:00
Carlo Caione
34e0294652 arm: aarch32: Use proper sys functions for cache mainteinance
This patchset is fixing two things:

1. The proper sys_* functions are used for cache mainteinance
   operations.

2. To check the status of the L1 cache the SCB registers are probed so
   the code is assuming a core architecture cache is present, thus make
   the code conditionally compiled on CONFIG_ARCH_CACHE.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-01-10 18:22:32 -05:00
Piotr Jasiński
7fa0af01cf Kconfig: add config for low-priority debug mon isr
Debug monitor needs to be configured to a low priority in order to be
useful for debugging (to prioritize other interrupts when waiting on a
breakpoint).
Added a config that configures the interrupt this way.

Signed-off-by: Piotr Jasiński <piotr.jasinski@nordicsemi.no>
2022-12-28 12:00:46 +01:00
Piotr Jasiński
1fe4b1eb90 linker: make debug monitor isr symbol weak
It seems that currently it's impossible to create a custom
implementation for debug monitor exception without updating the vector
table (z_arm_debug_monitor maps to fault).
My proposition is to make this symbol weak, so that it can be overriden.

Signed-off-by: Piotr Jasiński <piotr.jasinski@nordicsemi.no>
2022-12-28 12:00:46 +01:00
Duong Vu Nam
84b5d39cb6 arm: aarch32: config static regions with MPU disabled
There is the possibility that when reconfiguring the static regions,
some data that must be accessed is temporarily not accesible due to the
change on the MPU regions configuration. Workaround by disabling MPU
when doing the reconfiguration, same as with dynamic regions, until BR
can be enabled.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Duong Vu Nam
47cce0573e arch: update alignment for Cortex-R52
Cortex-R52 doesn't require power of 2 alignment

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Duong Vu Nam
b24f4625f0 arch: support nocache for Cortex-R52
Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.

Enable nocache in each driver use it.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Duong Vu Nam
ee639b64c3 arch: aarch32: add caches capability to Cortex-R52
Support I/D cache for Cortex-R52 to run with cache on NXP S32Z/E.
Make sure no data is present in the D-Cache before initializing mpu

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Carlo Caione
c96313ec3f arm: cache: Rework cache API
And use the new API.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-01 13:40:56 -05:00
Carlo Caione
189cd1f4a2 cache: Rework cache API
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.

In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.

In particular this changeset is doing three things:

1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
   `CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`

2. The cache API has been reworked.

3. Comments are added.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-01 13:40:56 -05:00
Wilfred Mallawa
7ac69dc4ca arch/arm/core: fixup typo
Fixup trivial typo.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@gmail.com>
2022-11-27 12:11:44 +01:00
Théophile Ranquet
6d8100424a arm: set low exception vector location
The code in prep_c sets VBAR to relocate vector from 0x0, assuming the
low vector bit in SCTLR to be clear. This isn't the case on all
hardware, so set it explicitly to support those.

Signed-off-by: Théophile Ranquet <theophile.ranquet@gmail.com>
2022-11-23 11:36:26 +01:00
Benjamin Gwin
b5fe0f7304 arch: arm: mpu: Add support for disabling the background address map
Arm provides a default address map defining default behaviors for
certain address ranges, which can be overlayed with additional regions
in the MPU. Users may also turn off this background map, so that only
regions explicitly programmed in the MPU are allowed.

This provides a Kconfig so that platforms using a non-standard address
map may disable the background address map and provide their own
explicit MPU regions.

Signed-off-by: Benjamin Gwin <bgwin@google.com>
2022-11-16 11:21:06 +01:00
Andrzej Głąbek
6578b218ca arch: arm: aarch32: cortex_m: fault: Fix SCB->CFSR access helpers
This is a follow-up to commit f400c94adf.

Fix typos in names of introduced macros (*STR -> *SR) and cast their
values to uint32_t to avoid warnings reported for messages formatted
with %x.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-11-11 08:56:18 +00:00
Kumar Gala
c778eb2a56 smp: Move arrays to use CONFIG_MP_MAX_NUM_CPUS
Move to use CONFIG_MP_MAX_NUM_CPUS for array size declarations instead
of CONFIG_MP_NUM_CPUS.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-10-17 14:40:12 +09:00
Anas Nashif
3d85ae37b6 arm: add missing includes
Add missing includes that were previously included indirectly.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 18:37:53 -04:00
Gerard Marull-Paretas
ac63bca423 include: add missing sys_clock.h include
Some headers made use of types defined in sys_clock.h (e.g. k_timeout_t)
without including it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Peter Marheine
5eb75b81f7 arm: rename default RAM region from 'SRAM' to 'RAM'
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-10-03 10:09:53 +02:00
Enjia Mai
d9206aa29b arch: arm: userspace: fix the incorrect ssf under bad syscall
The parameter ssf of the handler_bad_syscall got null pointer
due to that the R1 does not push into the stack in a right
order on cortex-M0. Adjust the pushing order of stack to make
the ssf being passed correctly.

Fixes #50146.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-09-19 09:17:26 +02:00
Gerard Marull-Paretas
79e6b0e0f6 includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.

The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.

NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-09-05 16:31:47 +02:00
Stephanos Ioannidis
8506979f27 arch: arm: mpu: Fix -Wstringop-overread warning
GCC 12 performs bounds checking on the pointer arguments specified like
an array (e.g. `int arg[]`) and treats such arguments with an empty
length as having the length of 0, resulting in the compiler printing
out `stringop-overread' warning when they are accessed.

This commit corrects any pointer arguments declared using the array
expression to use the pointer expression instead.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-08-25 22:29:28 +09:00
Peter Marheine
c30833da3a arch: move CODE_DATA_RELOCATION to top level
Support for CODE_DATA_RELOCATION is not inherently limited to ARM, so
move the Kconfig definition to top-level so it can be used by other
architectures. Since support is opt-in (requiring linker script
support), add a helper symbol enabled by architecture config that gates
whether CODE_DATA_RELOCATION is available instead of listing all
supported systems inline.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-24 10:08:06 +02:00